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STM32L496QGI3 Datasheet(PDF) 199 Page - STMicroelectronics |
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STM32L496QGI3 Datasheet(HTML) 199 Page - STMicroelectronics |
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199 / 262 page ![]() DocID029173 Rev 1 199/262 STM32L496xx Electrical characteristics 235 6.3.25 DFSDM characteristics Unless otherwise specified, the parameters given in Table 90 for DFSDM are derived from tests performed under the ambient temperature, fAPB2 frequency and VDD supply voltage conditions summarized in Table 22: General operating conditions. • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (DFSDM1_CKINy, DFSDM1_DATINy, DFSDM1_CKOUT for DFSDM). V44 Segment/Common highest level voltage - VLCD - V V34 Segment/Common 3/4 level voltage - 3/4 VLCD - V23 Segment/Common 2/3 level voltage - 2/3 VLCD - V12 Segment/Common 1/2 level voltage - 1/2 VLCD - V13 Segment/Common 1/3 level voltage - 1/3 VLCD - V14 Segment/Common 1/4 level voltage - 1/4 VLCD - V0 Segment/Common lowest level voltage - 0 - 1. Guaranteed by design. 2. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD connected. Table 89. LCD controller characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit Table 90. DFSDM characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fDFSDMCLK DFSDM clock - - - fSYSCLK MHz fCKIN (1/TCKIN) Input clock frequency SPI mode (SITP[1:0] = 01) - - 20 (fDFSDMCLK/4) fCKOUT Output clock frequency -- - 20 MHz DuCyCKOUT Output clock frequency duty cycle -45 50 55 % |
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