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STM32L496QGI3 Datasheet(PDF) 210 Page - STMicroelectronics |
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STM32L496QGI3 Datasheet(HTML) 210 Page - STMicroelectronics |
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210 / 262 page ![]() Electrical characteristics STM32L496xx 210/262 DocID029173 Rev 1 SAI characteristics Unless otherwise specified, the parameters given in Table 98 for SAI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage condi- tions summarized inTable 22: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 ₓ VDD Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (CK,SD,FS). Table 98. SAI characteristics(1) Symbol Parameter Conditions Min Max Unit fMCLK SAI Main clock output - - 50 MHz fCK SAI clock frequency(2) Master transmitter 2.7 V ≤ VDD ≤ 3.6 V Voltage Range 1 -21.5 MHz Master transmitter 1.71 V ≤ VDD ≤ 3.6 V Voltage Range 1 -13.5 Master receiver Voltage Range 1 -25 Slave transmitter 2.7 V ≤ VDD ≤ 3.6 V Voltage Range 1 -20 Slave transmitter 1.71 V ≤ VDD ≤ 3.6 V Voltage Range 1 -13.5 Slave receiver Voltage Range 1 -25 Voltage Range 2 - 13 1.08 V ≤ VDD ≤ 1.32 V - 7 tv(FS) FS valid time Master mode 2.7 V ≤ VDD ≤ 3.6 V -22 ns Master mode 1.71 V ≤ VDD ≤ 3.6 V -40 th(FS) FS hold time Master mode 10 - ns tsu(FS) FS setup time Slave mode 1 - ns th(FS) FS hold time Slave mode 2 - ns tsu(SD_A_MR) Data input setup time Master receiver 1 - ns tsu(SD_B_SR) Slave receiver 1 - th(SD_A_MR) Data input hold time Master receiver 5 - ns th(SD_B_SR) Slave receiver 2 - |
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