AFE5803 datasheet(48/53 Pages) TI2

48 / 53 page

AFE5803

SLOS763A

– JANUARY 2012 – REVISED JANUARY 2012

www.ti.com

POWER SUPPLY, GROUNDING AND BYPASSING

In a mixed-signal system design, power supply and grounding design plays a significant role. The AFE5803

distinguishes between two different grounds: AVSS(Analog Ground) and DVSS(digital ground). In most cases, it

should be adequate to lay out the printed circuit board (PCB) to use a single ground plane for the AFE5803.

Care should be taken that this ground plane is properly partitioned between various sections within the system to

minimize interactions between analog and digital circuitry. Alternatively, the digital (DVDD) supply set consisting

of the DVDD and DVSS pins can be placed on separate power and ground planes. For this configuration, the

AVSS and DVSS grounds should be tied together at the power connector in a star layout. In addition, optical

isolator or digital isolators, such as ISO7240, can separate the analog portion from the digital portion completely.

Consequently they prevent digital noise to contaminate the analog portion. Table 11 lists the related circuit blocks

for each power supply.

Table 12. Supply vs Circuit Blocks

POWER SUPPLY

GROUND

CIRCUIT BLOCKS

LNA, attenuator, PGA with current clamp

AVDD (3.3VA)

AVSS

and BPF, reference circuits, PGA test mode

buffer, VCA SPI

AVDD_5V (5VA)

AVSS

LNA, reference circuits

AVDD_ADC (1.8VA)

AVSS

ADC analog and reference circuits

DVDD (1.8VD)

DVSS

LVDS and ADC SPI

All Bypassing and power supplies for the AFE5803 should be referenced to their corresponding ground planes.

All supply pins should be bypassed with 0.1

µF ceramic chip capacitors (size 0603 or smaller). In order to

minimize the lead and trace inductance, the capacitors should be located as close to the supply pins as possible.

Where double-sided component mounting is allowed, these capacitors are best placed directly under the

package. In addition, larger bipolar decoupling capacitors 2.2

µF to 10 µF, effective at lower frequencies) may

also be used on the main supply pins. These components can be placed on the PCB in proximity (

< 0.5 in or

12.7 mm) to the AFE5803 itself.

The AFE5803 has a number of reference supplies needed to be bypassed, such CM_BYP, VHIGH, and

VREF_IN. These pins should be bypassed with at least 1

µF; higher value capacitors can be used for better

low-frequency noise suppression. For best results, choose low-inductance ceramic chip capacitors (size 0402,

µF) and place them as close as possible to the device pins.

High-speed mixed signal devices are sensitive to various types of noise coupling. One primary source of noise is

the switching noise from the serializer and the output buffer/drivers. For the AFE5803, care has been taken to

ensure that the interaction between the analog and digital supplies within the device is kept to a minimal amount.

The extent of noise coupled and transmitted from the digital and analog sections depends on the effective

inductances of each of the supply and ground connections. Smaller effective inductance of the supply and

ground pins leads to improved noise suppression. For this reason, multiple pins are used to connect each supply

and ground sets. It is important to maintain low inductance properties throughout the design of the PCB layout by

use of proper planes and layer thickness.

BOARD LAYOUT

Proper grounding and bypassing, short lead length, and the use of ground and power-supply planes are

particularly important for high-frequency designs. Achieving optimum performance with a high-performance

device such as the AFE5803 requires careful attention to the PCB layout to minimize the effects of board

parasitics and optimize component placement. A multilayer PCB usually ensures best results and allows

convenient component placement. In order to maintain proper LVDS timing, all LVDS traces should follow a

controlled impedance design. In addition, all LVDS trace lengths should be equal and symmetrical; it is

recommended to keep trace length variations less than 150mil (0.150 in or 3.81mm).

Additional details on BGA PCB layout techniques can be found in the Texas Instruments Application Report

MicroStar BGA Packaging Reference Guide (SSYZ015B), which can be downloaded from www.ti.com.

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