AFE5803 datasheet(5/53 Pages) TI2

5 / 53 page

AFE5803

www.ti.com

SLOS763A

– JANUARY 2012 – REVISED JANUARY 2012

PIN FUNCTIONS (continued)

DESCRIPTION

NO.

NAME

DCLKP

LVDS bit clock (7x) positive output

F8, F9, G8, G9,

K7,

DNC

Do not connect. Must leave floated

L5~L7,M5~M8,

N4, N6

N3, N7

DVDD

ADC digital and I/O power supply, 1.8 V

N5, P5, R5

DVSS

ADC digital ground

FCLKM

LVDS frame clock (1X) negative output

FCLKP

LVDS frame clock (1X) positive output

CH1~8 complimentary analog inputs. Bypass to ground with

≥ 0.015 µF capacitors. The HPF response

C9~C2

INM1

…INM8

of the LNA depends on the capacitors.

A9~A2

INP1...INP8

CH1~8 analog inputs. AC couple to inputs with

≥ 0.1µF capacitors.

PDN_ADC

ADC partial (fast) power down control pin with an internal pull down resistor of 100 k

Ω. Active High.

PDN_VCA

VCA partial (fast) power down control pin with an internal pull down resistor of 20 k

Ω. Active High.

Global (complete) power-down control pin for the entire chip with an internal pull down resistor of 20k

Ω.

PDN_GLOBAL

Active High.

0.5 V reference output in the internal reference mode. Must leave floated in the internal reference mode.

REFM

Adding test point on PCB is recommended for monitoring the reference output.

1.5 V reference output in the internal reference mode. Must leave floated in the internal reference mode.

REFP

Adding test point on PCB is recommended for monitoring the reference output.

RESET

Hardware reset pin with an internal pull-down resistor of 20 k

Ω. Active high.

SCLK

Serial interface clock input with an internal pull-down resistor of 2 0k

SDATA

Serial interface data input with an internal pull-down resistor of 20 k

SDOUT

Serial interface data readout. High impedance when readout is disabled.

SEN

Serial interface enable with an internal pull up resistor of 20 k

Ω. Active low.

VCNTLM

Negative differential attenuation control pin.

VCNTLP

Positive differential attenuation control pin

VHIGH

Bias voltage; bypass to ground with

≥1µF.

VREF_IN

ADC 1.4 V reference input in the external reference mode; bypass to ground with 0. 1

µF.

F8, F9, G8, G9,

K7, L5~L7,

DNC

Do not connect. Must leave floated

M5~M8, N4,

Submit Documentation Feedback

Product Folder Link(s): AFE5803

AFE5803 Datasheet(PDF) 5 Page - Texas Instruments

AFE5803 Datasheet(HTML) 5 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Datasheet Download

Link URL