MUX507IPWR datasheet(31/43 Pages) TI2

31 / 43 page

Via to

GND Plane

Via to

GND Plane

Via to

GND Plane

VDD

S16

S15

S14

S13

S12

S11

S10

GND

VSS

MUX506IPW

MUX506, MUX507

www.ti.com

SBAS803A – NOVEMBER 2016 – REVISED NOVEMBER 2017

Product Folder Links: MUX506 MUX507

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11 Layout

11.1 Layout Guidelines

Figure 45 illustrates an example of a PCB layout with the MUX506IPW, and Figure 46 illustrates an example of a

PCB layout with MUX507IPW.

Some key considerations are:

1. Decouple the VDD and VSS pins with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure

that the capacitor voltage rating is sufficient for the VDD and VSS supplies.

2. Keep the input lines as short as possible. In case of the differential signal, make sure the A inputs and B

inputs are as symmetric as possible.

3. Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.

4. Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when necessary.

11.2 Layout Example

Figure 45. MUX506IPW Layout Example

MUX507IPWR Datasheet(PDF) 31 Page - Texas Instruments