AR0130CS

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28

Table 8. TWO-WIRE SERIAL BUS CHARACTERISTICS (continued)

(fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; TA = 25°C)

Parameter

Unit

Fast-Mode

Standard Mode

Symbol

Parameter

Unit

Max

Min

Max

Min

Symbol

Bus Free Time between a STOP

and START Condition

tBUF

4.7

−

1.3

−

ms

Capacitive Load for each Bus Line

Cb

−

400

−

400

pF

Serial Interface Input Pin Capaci-

tance

CIN_SI

−

3.3

−

3.3

pF

SDATA Max Load Capacitance

CLOAD_SD

−

30

−

30

pF

SDATA Pull-up Resistor

RSD

1.5

4.7

1.5

4.7

kW

1. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.

2. Two-wire control is I2C-compatible.

3. All values referred to VIHmin = 0.9 VDD_IO and VILmax = 0.1 VDD_IO levels. Sensor EXTCLK = 27 MHz.

4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of

SCLK.

5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.

6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This

will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW

period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Stan-

dard-mode I2C-bus specification) before the SCLK line is released.

7. Cb = total capacitance of one bus line in pF.

I/O Timing

By default, the AR0130 launches pixel data, FV and LV

with the falling edge of PIXCLK. The expectation is that the

user captures DOUT[11:0], FV and LV using the rising edge

of PIXCLK.

See Figure 29 and Table 9 for I/O timing (AC)

characteristics.

Figure 29. I/O Timing Diagram

EXTCLK

PIXCLK

Data[11:0]

LINE_VALID/

FRAME_VALID

Pxl_0

Pxl_1

Pxl_2

Pxl_n

tPFL

tPLL

tFP

tRP

tF

tR

90%

90%

90%

90%

10%

10%

10%

10%

tEXTCLK

tPD

tPLH

tPFH

FRAME_VALID Leads LINE_VALID

by 6 PIXCLKs

FRAME_VALID Trails LINE_VALID

by 6 PIXCLKs

Table 9. I/O TIMING CHARACTERISTICS (2.8 V VDD_IO) (Note 8)

Conditions: fPIXCLK = 74.25 MHz (720 P 60 fps) VDD_IO = 2.8 V;

Slew Rate Setting = 4 for PIXCLK; Slew Rate Setting = 7 for Parallel Ports

Symbol

Definition

Condition

Min

Typ

Max

Unit

fEXTCLK

Input Clock Frequency

PLL Enabled

6

−

50

MHz

tEXTCLK

Input Clock Period

PLL Enabled

20

−

166

ns

tR

Input Clock Rise Time

−

3

−

ns

tF

Input Clock Fall Time

−

3

−

ns