www.ti.com

Data Input

Data Input Address Bits

TLC2543-EP

12-BIT ANALOG-TO-DIGITAL CONVERTER

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SGLS125A – JULY 2002 – REVISED NOVEMBER 2006

The data input is internally connected to an 8-bit serial-input address and control register. The register defines

the operation of the converter and the output data length. The host provides the data word with the MSB first.

Each data bit is clocked in on the rising edge of the I/O CLOCK sequence (see Table 2 for the data

input-register format).

Table 2. Input-Register Format

INPUT DATA BYTE

ADDRESS BITS

L1

L0

LSBF

BIP

FUNCTION SELECT

D7

D0

D6

D5

D4

D3

D2

D1

(MSB)

(LSB)

Select input channel

AIN0

0

0

0

0

AIN1

0

0

0

1

AIN2

0

0

1

0

AIN3

0

0

1

1

AIN4

0

1

0

0

AIN5

0

1

0

1

AIN6

0

1

1

0

AIN7

0

1

1

1

AIN8

1

0

0

0

AIN9

1

0

0

1

AIN10

1

0

1

0

Select test voltage

(Vref+ – Vref–)/2

1

0

1

1

Vref–

1

1

0

0

Vref+

1

1

0

1

Software power down

1

1

1

0

Output data length

8 bits

0

1

12 bits

X(1)

0

16 bits

1

1

Output data format

MSB first

0

LSB first (LSBF)

1

Unipolar (binary)

0

Bipolar (BIP) 2s complement

1

(1)

The four MSBs (D7–D4) of the data register address one of the 11 input channels, a reference-test voltage, or the power-down mode.

The address bits affect the current conversion, which is the conversion that immediately follows the current I/O cycle. The reference

voltage is nominally equal to Vref+– Vref–.

The four MSBs (D7–D4) of the data register address 1 of the 11 input channels, a reference-test voltage, or the

power-down mode. The address bits affect the current conversion, which is the conversion that immediately

follows the current I/O cycle. The reference voltage is nominally equal to Vref+– Vref–.

14

Submit Documentation Feedback