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Chip-Select (CS) Input

Power-Down Features

Analog Input, Test, and Power-Down Mode

TLC2543-EP

12-BIT ANALOG-TO-DIGITAL CONVERTER

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SGLS125A – JULY 2002 – REVISED NOVEMBER 2006

CS enables and disables the device. During normal operation, CS should be low. Although the use of CS is not

necessary to synchronize a data transfer, it can be brought high between conversions to coordinate the data

transfer of several devices sharing the same bus.

When CS is brought high, the serial-data output is immediately brought to the high-impedance state, releasing

its output data line to other devices that may share it. After an internally generated debounce time, I/O CLOCK is

inhibited, thus preventing any further change in the internal state.

When CS is subsequently brought low again, the device is reset. CS must be held low for an internal debounce

time before the reset operation takes effect. After CS is debounced low, I/O CLOCK must remain inactive (low)

for a minimum time before a new I/O cycle can start.

CS can interrupt any ongoing data transfer or any ongoing conversion. When CS is debounced low long enough

before the end of the current conversion cycle, the previous conversion result is saved in the internal output

buffer and shifted out during the next I/O cycle.

When a binary address of 1110 is clocked into the input data register during the first four I/O CLOCK cycles, the

power-down mode is selected. Power down is activated on the falling edge of the fourth I/O CLOCK pulse.

During power down, all internal circuitry is put in a low-current standby mode. No conversions are performed,

and the internal output buffer keeps the previous conversion cycle data results provided that all digital inputs are

held above VCC – 0.5 V or below 0.5 V. The I/O logic remains active so the current I/O cycle must be completed,

even when the power-down mode is selected. Upon power-on reset and before the first I/O cycle, the converter

normally begins in the power-down mode. The device remains in the power-down mode until a valid input

address (other than 1110) is clocked in. Upon completion of that I/O cycle, a normal conversion is performed

with the results being shifted out during the next I/O cycle.

The 11 analog inputs, 3 internal voltages, and power-down mode are selected by the input multiplexer according

to the input addresses shown in Table 3, Table 4, and Table 5. The input multiplexer is a break-before-make

type to reduce input-to-input noise rejection resulting from channel switching. Sampling of the analog input starts

on the falling edge of the fourth I/O CLOCK and continues for the remaining I/O CLOCK pulses. The sample is

held on the falling edge of the last I/O clock pulse. The three internal test inputs are applied to the multiplexer,

then sampled and converted in the same manner as the external analog inputs. The first conversion after the

device has returned from the power-down state may not read accurately due to internal device settling.

Table 3. Analog-Channel-Select Address

VALUE SHIFTED INTO DATA INPUT

ANALOG INPUT

SELECTED

BINARY

HEX

AIN0

0000

0

AIN1

0001

1

AIN2

0010

2

AIN3

0011

3

AIN4

0100

4

AIN5

0101

5

AIN6

0110

6

AIN7

0111

7

AIN8

1000

8

AIN9

1001

9

AIN10

1010

A

17

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