DIX4192 datasheet(28/70 Pages) TI2

28 / 70 page

DIX4192-Q1

SBFS041A – JULY 2016 – REVISED APRIL 2017

www.ti.com

Product Folder Links: DIX4192-Q1

Submit Documentation Feedback

Figure 23. Register 01: Power-Down and Reset

7 (MSB)

0 (LSB)

RESET

PDALL

PDPA

PDPB

PDTX

PDRX

Table 4. Register 01: Power-Down and Reset Field Descriptions

PDRX

Power-Down for the Receiver Function Block

This bit is used to power-down the DIR and associated functions. All receiver outputs are forced low.

PDRX

Receiver Power-Down Mode

Enabled (default)

Disabled; the Receiver function block will operate normally based upon the applicable control register settings.

PDTX

Power-Down for the Transmitter Function Block

This bit is used to power-down the DIT and associated functions. All transmitter outputs are forced low.

PDTX

Transmitter Power-Down Mode

Enabled (default)

Disabled; the Transmitter function block will operate normally based upon the applicable control register settings.

PDPB

Power-Down for Serial Port B

This bit is used to power-down the audio serial I/O Port B. All port outputs are forced low.

PDPB

Port B Power-Down Mode

Enabled (default)

Disabled; Port B will operate normally based upon the applicable control register settings.

PDPA

Power-Down for Serial Port A

This bit is used to power-down the audio serial I/O Port A. All port outputs are forced low.

PDPA

Port A Power-Down Mode

Enabled (default)

Disabled; Port A will operate normally based upon the applicable control register settings.

PDALL

Power-Down for All Functions

This bit is used to power-down all function blocks except the host interface port and the control and status registers.

PDALL

All Function Power-Down Mode

Enabled (default)

Disabled; all function blocks will operate normally based upon the applicable control register settings.

RESET

Software Reset

This bit is used to force a reset initialization sequence, and is equivalent to forcing an external reset through the RST input (pin 24).

RESET

Reset Function

Disabled (default)

Enabled; all control registers will be reset to the default state.

Figure 24. Register 02: Global Interrupt Status (Read-Only)

7 (MSB)

0 (LSB)

Table 5. Register 02: Global Interrupt Status (Read-Only) Field Descriptions

Receiver Function Block Interrupt Status (Active High)

When set to 1, this bit indicates an active interrupt from the DIR function block. This bit is active high. The user must then read status

registers 0x14 and 0x15 in order to determine which of the sources has generated an interrupt.

Transmitter Function Block Interrupt Status (Active High)

When set to 1, this bit indicates an active interrupt from the DIT function block. This bit is active high. The user must then read status

DIX4192 Datasheet(PDF) 28 Page - Texas Instruments

DIX4192 Datasheet(HTML) 28 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Datasheet Download

Link URL