DIX4192 datasheet(46/70 Pages) TI2

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DIX4192-Q1

SBFS041A – JULY 2016 – REVISED APRIL 2017

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Figure 68. Register 7F: Page Selection Register

7 (MSB)

0 (LSB)

PAGE1

PAGE0

Table 34. Register 7F: Page Selection Register Field Descriptions

PAGE[1:0]

Page Selection

These bits are used to select one of three register pages for write and/or read access through the SPI or I2C serial host interface. The

Page Selection Register is present on every register page at address 0x7F, allowing movement between pages as necessary.

PAGE1

PAGE0

Page 0, control and status registers (default)

Page 1, DIR channel status and user data buffers

Page 2, DIT channel status and user data buffers

Page 3, reserved

9.5.3 Channel Status and User Data Buffer Maps

Table 35 through Table 38 show the buffer maps for the DIR and DIT channel status and user data buffers.

For Table 35, the channel status byte definitions are dependent on the transmission mode, either Professional or

Consumer. Bit 0 of Byte 0 defines the transmission mode, 0 for Consumer mode, and 1 for Professional mode.

This is applicable for Table 35 and Table 36.

For Table 37, the channel status byte definitions are dependent on the transmission mode, either Professional or

Consumer. Bit 0 of Byte 0 defines the transmission mode, 0 for Consumer mode, and 1 for Professional mode. In

Professional mode, Byte 23 for each channel is reserved for CRC data, which is automatically calculated and

encoded by the DIT. There is no requirement to program Byte 23 for either channel in Professional mode.

DIX4192 Datasheet(PDF) 46 Page - Texas Instruments