DIX4192 datasheet(3/70 Pages) TI2

3 / 70 page

DIX4192-Q1

www.ti.com

SBFS041A – JULY 2016 – REVISED APRIL 2017

Product Folder Links: DIX4192-Q1

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5 Description (continued)

The DIX4192-Q1 device is configured using on-chip control registers and data buffers, which are accessed

through either a four-wire serial peripheral interface (SPI) port, or a two-wire I2C bus interface. Status registers

provide access to a variety of flag and error bits, which are derived from the various function blocks. An open-

drain interrupt output pin is provided, and is supported by flexible interrupt reporting and mask options through

control register settings. A master reset input pin is provided for initialization by a host processor or supervisory

functions.

The DIX4192-Q1 device requires a 1.8-V core logic supply, in addition to a 3.3-V supply for powering portions of

the DIR, DIT, and line driver and receiver functions. A separate logic I/O supply supports operation from 1.65 V

to 3.6 V, providing compatibility with low-voltage logic interfaces typically found on digital signal processors and

programmable logic devices.

The DIX4192-Q1 device is available in a lead-free, TQFP-48 package.

6 Device Comparison Table

PART NUMBER

1.8-V I/O

MULTI-CH PCM

ADC

PCM PORTS

S/PDIF PORTS

DIX4192-Q1

Yes

4 differential line in and 1

differential line out

PCM9211

Yes

Up to 3 in and up to 3

out

Up to 12 single-ended in

and up to 2 single-ended

out

DIX9211

Yes

Up to 3 in and up to 3

out

Up to 12 single-ended in

and up to 2 single-ended

out

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