DIX4192 datasheet(7/70 Pages) TI2

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DIX4192-Q1

www.ti.com

SBFS041A – JULY 2016 – REVISED APRIL 2017

Product Folder Links: DIX4192-Q1

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Electrical Characteristics (continued)

all specifications are at TA = 25°C, VDD18 = 1.8 V, VDD33 = 3.3 V, VIO = 3.3 V, and VCC = 3.3 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(1)

The typical VIO supply current is measured using the DIX4192-Q1EVM evaluation module with loading from the DAIMB motherboard

circuitry. VIO supply current is dependent upon the loading on the logic output pins.

PLL lock range

TA = 25°C

216

kHz

TA = 85°C or 105°C

216

fRXCKI

Reference clock input (RXCKI) frequency

3.5

27.7

MHz

fRXCKID

Reference clock input (RXCKI) duty cycle

45%

55%

fRXCKO

Recovered clock output (RXCKO) frequency

3.5

27.7

MHz

fRXCKOD Recovered clock output (RXCKO) duty cycle

45%

55%

Recovered clock output (RXCKO) intrinsic

jitter

Measured cycle-to-cycle

250

ps RMS

DIGITAL AUDIO INTERFACE TRANSMITTER (DIT)

Intrinsic output jitter

Measured cycle-to-cycle

200

ps RMS

POWER SUPPLIES

Supply current: initial startup

All blocks powered down by default

IDD18S

VDD18 = 1.8 V

μA

IDD33S

VDD33 = 3.3 V

IIOS

VIO = 3.3 V

300

ICCS

VCC = 3.3 V

Supply current: quiescent

All blocks powered up with no clocks applied

IDD18Q

VDD18 = 1.8 V

2.3

IDD33Q

VDD33 = 3.3 V

0.6

IIOQ

VIO = 3.3 V

0.3

ICCQ

VCC = 3.3 V

6.3

Supply current: dynamic

All blocks powered up, fS = 48 kHz

IDD18D

VDD18 = 1.8 V

5.1

IDD33D

VDD33 = 3.3 V

14.1

IIOD(1)

VIO = 3.3 V

ICCD

VCC = 3.3 V

7.4

Supply current: high sampling rate

All blocks powered up, fS = 192 kHz

IDD18H

VDD18 = 1.8 V

6.7

IDD33H

VDD33 = 3.3 V

IIOH(1)

VIO = 3.3 V

ICCH

VCC = 3.3 V

7.5

Total power dissipation: initial startup

All blocks powered down by default

Total power dissipation: quiescent

All blocks powered up with no clocks applied

Total power dissipation: dynamic

All blocks powered up, fS = 48 kHz

233

Total power dissipation: high sampling rate

All blocks powered up, fS = 192 kHz

242

8.6 Timing Requirements

MIN

NOM

MAX

UNIT

AUDIO SERIAL PORTS (PORT A AND PORT B)

fLRCK

LRCK clock frequency

216

kHz

tLRCKD

LRCK clock duty cycle

50%

fBCK

BCK clock frequency

13.824

MHz

tBCKH

BCK high pulse duration

tBCKL

BCK low pulse duration

tAIS

Audio data Input (SDIN) set-up time

tAISH

Audio data input (SDIN) hold time

tADD

Audio data output (SDOUT) delay

DIX4192 Datasheet(PDF) 7 Page - Texas Instruments

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