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DETAILED DESCRIPTION

HIGH-SPEED DATA PATH

BANDGAP VOLTAGE AND BIAS GENERATION

HIGH-SPEED OUTPUT BUFFER

RATE SELECT

ONET8501P

SLLS885 – FEBRUARY 2008

AC ELECTRICAL CHARACTERISTICS (continued)

Over recommended operating conditions, outputs connected to a 50-

Ω load, AMP1 = 0, AMP0 = 1 (Register 3) and maximum

bandwidth unless otherwise noted. Typical operating condition is at VCC = 3.3 V and TA = +25°C

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

TDIS

Disable response time

20

ns

The high-speed data signal is applied to the data path by means of input signal pins DIN+/DIN–. The data path

consists of a 100-

Ω differential on-chip line termination resistor followed by a digitally controlled bandwidth switch

input buffer for rate select. The RATE1 and RATE0 pins can be used to control the bandwidth of the filter.

Default bandwidth settings are used; however, these can be changed using registers 4 through 7 via the serial

interface. For details regarding the rate selection, see Table 19. A gain stage and an output buffer stage follow

the input buffer, which together provide a gain of 40dB. The device can accept input amplitude levels from 5

mVpp up to 2000 mVpp. The amplified data output signal is available at the output pins DOUT+/DOUT– which

include on-chip 2

× 50-Ω back-termination to VCC.

Offset cancellation compensates for internal offset voltages and thus ensures proper operation even for very

small input data signals. The offset cancellation can be disabled so that the input threshold voltage can be

adjusted to optimize the bit error rate or change the eye crossing to compensate for input signal pulse width

distortion. The offset cancellation can be disabled by setting OCDIS = 1 (bit 1 of register 0). The input threshold

level can be adjusted using register settings THADJ[0..7] (register 1). For details regarding input threshold adjust,

see Table 19.

The low frequency cutoff is as low as 80 kHz with the built-in filter capacitor. For applications, which require even

lower cutoff frequencies, an additional external filter capacitor may be connected to the COC1 and COC2 pins. A

value of 330 pF results in a low frequency cutoff of 20 kHz.

The ONET8501P limiting amplifier is supplied by a single +3.3-V supply voltage connected to the VCC pins. This

voltage is referred to ground (GND).

On-chip bandgap voltage circuitry generates a reference voltage, independent of supply voltage, from which all

other internally required voltages and bias currents are derived.

The output amplitude of the buffer can be set to 300 mVpp, 600 mVpp or 900 mVpp using register settings

AMP[0..1] (register 3) via the serial interface. To compensate for frequency dependant losses of transmission

lines connected to the output, the ONET8501P has adjustable pre-emphasis of the output stage. The

pre-emphasis can be set from 0 to 8 dB in 1 dB steps using register settings PEADJ[0..3] (register 2).

There are 16 possible internal filter settings (4 bit) to adjust the small signal bandwidth to the data rate. For fast

rate selection, 4 default values can be selected with the RATE1 and RATE0 pins. Using the serial interface, the

bandwidth settings can be customized instead of using the default values. The default bandwidths and the

registers used to change the bandwidth settings are shown in Table 1.

Table 1. Rate Selection Default Settings and Registers Used for Adjustment

RATE1

RATE0

DEFAULT BANDWIDTH

REGISTER USED FOR ADJUSTMENT

(GHz)

0

0

2.2

RSA (Register 4)

0

1

4.0

RSB (Register 5)

1

1

6.5

RSC (Register 6)

1

0

11.0

RSD (Register 7)

6

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