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P

S

S

P

SDA

SCK

t

BUF

t

LOW

t

SUSTA

t

HIGH

t

HDSTA

t

r

t

HDSTA

t

HDSTA

t

SUDAT

t

SUSTO

t

f

T0295-01

S

SDA

SCK

P

1–7

1–7

1–7

SLAVE

ADDRESS

R/W

ACK

8

9

8

9

REGISTER

ADDRESS

ACK

8

9

ACK

REGISTER

FUNCTION

T0296-01

REGISTER MAPPING

ONET8501P

SLLS885 – FEBRUARY 2008

Figure 3. I2C Timing Diagram

Table 4. Timing Diagram Definitions

PARAMETER

MIN

MAX

UNIT

fSCK

SCK clock frequency

400

kHz

tBUF

Bus free time between START and STOP conditions

1.3

µs

tHDSTA

Hold time after repeated START condition. After this period, the first clock pulse is generated

0.6

µs

tLOW

Low period of the SCK clock

1.3

µs

tHIGH

High period of the SCK clock

0.6

µs

tSUSTA

Setup time for a repeated START condition

0.6

µs

tHDDAT

Data HOLD time

0

µs

tSUDAT

Data setup time

100

ns

tR

Rise time of both SDA and SCK signals

300

ns

tF

Fall time of both SDA and SCK signals

300

ns

tSUSTO

Setup time for STOP condition

0.6

µs

Figure 4. I2C Data Transfer

The register mapping for read/write register addresses 0 (0x00) through 11 (0x0B) are shown in Table 5 through

Table 16. The register mapping for the read only register addresses 14 (0x0E) and 15 (0x0F) are shown in

Table 17 and Table 18.

Table 19 describes the circuit functionality based on the register settings.

Copyright © 2008, Texas Instruments Incorporated

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