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2-WIRE INTERFACE AND CONTROL LOGIC

ONET8501P

SLLS885 – FEBRUARY 2008

If the LOS register selection bit is set LOW, for example LOSASEL = 0 (bit 7, register 8), then the default LOS

assert level for that register is used. If the register selection bit is set HIGH, for example LOSASEL = 1 (bit 7,

register 8), then the content of LOSA[0..6] (register 8) is used to set the LOS assert level when RATE1 = 0 and

RATE0 = 0. The RATE1 and RATE0 pins do not have to be used if the serial interface is being used. If RATE1 is

not connected it is internally pulled HIGH and if RATE0 is not connected it is internally pulled LOW, thus

selecting register 11. Therefore, changing the contents of LOSD[0..6] (register 11) through the serial interface

can be used to adjust the LOS assert level.

The ONET8501P uses a 2-wire serial interface for digital control. The two circuit inputs, SDA and SCK, are

driven, respectively, by the serial data and serial clock from a microcontroller, for example. Both inputs include

100-k

Ω pull-up resistors to VCC. For driving these inputs, an open drain output is recommended.

The 2-wire interface allows write access to the internal memory map to modify control registers and read access

to read out control and status signals. The ONET8501P is a slave device only which means that it can not initiate

a transmission itself; it always relies on the availability of the SCK signal for the duration of the transmission. The

master device provides the clock signal as well as the START and STOP commands. The protocol for a data

transmission is as follows:

1. START command

2. 7-bit slave address (1000100) followed by an eighth bit which is the data direction bit (R/W). A zero indicates

a WRITE and a 1 indicates a READ.

3. 8-bit register address

4. 8-bit register data word

5. STOP command

Regarding timing, the ONET8501P is I2C compatible. The typical timing is shown in Figure 3 and a complete

data transfer is shown in Figure 4. Parameters for Figure 3 are defined in Table 4.

Bus Idle: Both SDA and SCK lines remain HIGH

Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCK line is HIGH,

defines a START condition (S). Each data transfer begins with a START condition.

Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCK line is HIGH

defines a STOP condition (P). Each data transfer ends with a STOP condition; however, if the master still wishes

to communicate on the bus, it can generate a repeated START condition and address another slave without first

generating a STOP condition.

Data Transfer: Only one data byte can be transferred between a START and a STOP condition. The receiver

acknowledges the transfer of data.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledgment bit. The

transmitter releases the SDA line and a device that acknowledges, must pull down the SDA line during the

acknowledge clock pulse simultaneously so the SDA line is stable LOW during the HIGH period of the

acknowledge clock pulse. Set-up and hold times must be taken into account. When a slave-receiver fails to

acknowledge the slave address, the data line must be left HIGH by the slave. The master can generate a STOP

condition to prevent the transfer. If the slave-receiver does acknowledge the slave address but some time later in

the transfer cannot receive any more data bytes, the master must cancel the transfer. This is indicated by the

slave generating the not acknowledge on the first following byte. The slave leaves the data line HIGH and the

master generates the STOP condition.

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