Power Dissipation (W)

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D028

TLV733 DQN, High-K Layout

TLV733 DBV, High-K Layout

17

TLV733P

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SBVS235C – OCTOBER 2014 – REVISED JULY 2019

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Application Information (continued)

8.1.2 Dropout Voltage

The TLV733 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout

voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the

RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device

behaves like a resistor in dropout mode. As with any linear regulator, PSRR and transient response degrade as

(VIN – VOUT) approaches dropout operation. See Figure 7 to Figure 12 for typical dropout values.

8.1.3 Power Dissipation

The ability to remove heat from the die is different for each package type, presenting different considerations in

the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves

the heat from the device to ambient air. Performance data for JEDEC high-K boards are given in the Thermal

Information table. Using heavier copper increases the effectiveness in removing heat from the device. The

addition of plated through-holes to heat-dissipating layers also improves heatsink effectiveness.

Power dissipation (PD) depends on input voltage and load conditions. PD is equal to the product of the output

current and voltage drop across the output pass element, as shown in Equation 2.

PD = (VIN – VOUT) × IOUT

(2)

Figure 34 shows the maximum ambient temperature versus the power dissipation of the TLV733 in the DQN and

DBV packages. This figure assumes the device is soldered on JEDEC standard high-K layout with no airflow

over the board. Actual board thermal impedances vary widely. If the application requires high power dissipation,

having a thorough understanding of the board temperature and thermal impedances is helpful to make sure the

TLV733 does not operate continuously above a junction temperature of 125°C.

TLV733, high-K layout

Figure 34. Maximum Ambient Temperature vs Device Power Dissipation