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GROUNDING AND PowerPAD LAYOUT

LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE

Minimum Recommended Exposed

Copper Area For Powerpad. 5mm

Stencils may Require 10 Percent

Larger Area

0.2454

0.0150

0.06

0.0256

0.1700

0.1340

0.0620

0.0400

0.0400

0.0400

0.0600

0.0227

0.0600

0.1010

6 PL

∅ 0.0130

4 PL

∅ 0.0180

Connect Pin 1 to Analog Ground Plane

in This Area for Optimum Performance

Minimum Recommended Top

Side Analog Ground Area

Minimum Recommended Thermal Vias: 6

× .013 dia.

Inside Powerpad Area 4

× .018 dia. Under Device as Shown.

Additional .018 dia. Vias May be Used if Top Side Analog

Ground Area is Extended.

0.2560

TPS54311-EP, TPS54312-EP,

TPS54313-EP, TPS54314-EP,

TPS54315-EP, TPS54316-EP

SGLS376A – FEBRUARY 2007 – REVISED MARCH 2007

APPLICATION INFORMATION (continued)

The TPS54311-16 has two internal grounds (analog and power). Inside the TPS54311-16, the analog ground

ties to all of the noise sensitive signals, while the power ground ties to the noisier power signals. The PowerPAD

must be connected directly to AGND. Noise injected between the two grounds can degrade the performance of

the TPS54311-16, particularly at higher output currents. However, ground noise on an analog ground plane can

also cause problems with some of the control and bias signals. For these reasons, separate analog and power

ground planes are recommended. These two planes should tie together directly at the IC to reduce noise

between the two grounds. The only components that should tie directly to the power ground plane are the input

capacitor, the output capacitor, the input voltage decoupling capacitor, and the PGND pins of the TPS54311-16.

The layout of the TPS54311-16 evaluation module is representative of a recommended layout for a 4-layer

board. Documentation for the TPS54311-16 evaluation module can be found on the Texas Instruments web site

under the TPS54311-16 product folder and in the application note, Texas Instruments literature number

SLVA111.

For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A

3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient

temperature and airflow. Most applications have larger areas of internal ground plane available, and the

PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also

help dissipate heat, and any area available should be used when 3 A or greater operation is desired. Connection

from the exposed area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch

diameter vias to avoid solder wicking through the vias. Six vias should be in the PowerPAD area with four

additional vias located under the device package. The size of the vias under the package, but not in the exposed

thermal pad area, can be increased to 0.018. Additional vias beyond the ten recommended that enhance

thermal performance should be included in areas not under the device package.

Figure 11. Recommended Land Pattern for 20-Pin PWP PowerPAD

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