STM32U073RCT3 datasheet(81/146 Pages) STMICROELECTRONICS

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Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually

forcing a low state on the NRST pin or the Oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values.

When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring

(see application note AN1015).

Electromagnetic Interference

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2

LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test

board and the pin loading.

Table 60. EMI characteristics for fHSE = 8 MHz and fHCLK = 54 MHz

Symbol

Parameter

Conditions

Monitored frequency band

Value

Unit

SEMI

Peak

VDD = 3.6 V, TA = 25 °C,

LQFP64 package

compliant with IEC 61967-2

0.1 MHz to 30 MHz

dBµV

30 MHz to 130 MHz

130 MHz to 1 GHz

1 GHz to 2 GHz

Level

0.1 MHz to 2 GHz

1. Refer to AN1709 “EMI radiated test” section.

2. Refer to AN1709 “EMI level classification” section.

6.3.12

Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to

determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each

sample according to each pin combination. The sample size depends on the number of supply pins in the device

(3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard.

Table 61. ESD absolute maximum ratings

TBD stands for "to be defined".

Symbol

Ratings

Conditions

Package Class

Maximum

value

Unit

VESD(HBM)

Electrostatic discharge voltage

(human body model)

TA = +25 °C, conforming to ANSI/ESDA/JEDEC

JS-001

All

2000

VESD(CDM)

Electrostatic discharge voltage

(charge device model)

TA = +25 °C, conforming to ANSI/ESDA/

JEDEC-002

WLCSP42

TBD

All others

C2a

500

1. Evaluated by characterization, not tested in production.

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

•

A supply overvoltage is applied to each power supply pin.

•

A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78A IC latch-up standard.

STM32U073x8/B/C

Electrical characteristics

DS14548 - Rev 2

page 81/146

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