STM32U073RCT3 datasheet(18/146 Pages) STMICROELECTRONICS

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If a higher-priority interrupt event happens while a lower-priority interrupt event occurring just before is waiting for

being served, the later-arriving higher-priority interrupt event is served first. Another optimization is called tail-

chaining. Upon a return from a higher-priority ISR then start of a pending lower-priority ISR, the unnecessary

processor context unstacking and stacking is skipped. This reduces latency and contributes to power efficiency.

Features of the NVIC:

•

Low-latency interrupt processing

•

Four priority levels

•

Handling of a non-maskable interrupt (NMI)

•

Handling of 32 maskable interrupt lines

•

Handling of 10 Cortex-M0+ exceptions

•

Later-arriving higher-priority interrupt processed first

•

Tail-chaining

•

Interrupt vector retrieval by hardware

3.14.2

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller adds flexibility in handling physical line events and allows identifying

wake-up events at processor wake-up from Stop mode.

The EXTI controller has a number of channels, of which some with rising, falling or rising, and falling edge

detector capability. Any GPIO and a few peripheral signals can be connected to these channels.

The channels can be independently masked.

The EXTI controller can capture pulses shorter than the internal clock period.

A register in the EXTI controller latches every event even in Stop mode, which enables the software to identify the

origin of the processor wake-up from Stop mode or, to identify the GPIO and the edge event having caused an

interrupt.

3.15

Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator

polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the

scope of the EN/IEC 60335-1 standard, they offer a means of verifying the flash memory integrity. The CRC

calculation unit helps compute a signature of the software during runtime, to be compared with a reference

signature generated at link time and stored at a given memory location.

3.16

Analog-to-digital converter (ADC)

A native 12-bit analog-to-digital converter is embedded into STM32U073x8/B/C devices. It can be extended to 16-

bit resolution through hardware oversampling. The ADC has up to 16 external channels and 3 internal channels

(temperature sensor, voltage reference, VBAT monitoring). It performs conversions in single-shot or scan mode. In

scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC frequency is independent from the CPU frequency, allowing maximum sampling rate of ~2 Msps even

with a low CPU speed. An auto-shutdown function guarantees that the ADC is powered off except during the

active conversion phase.

The ADC can be served by the DMA controller. It can operate in the whole VDD supply range.

The ADC features a hardware oversampler up to 256 samples, improving the resolution to 16 bits (refer to

AN2668).

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned

channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers,

to allow the application to synchronize A/D conversions with timers.

3.16.1

Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.

The temperature sensor is internally connected to an ADC input to convert the sensor output voltage into a digital

value.

STM32U073x8/B/C

Functional overview

DS14548 - Rev 2

page 18/146

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