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STM32U073RCT3 Datasheet(PDF) 15 Page - STMicroelectronics |
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STM32U073RCT3 Datasheet(HTML) 15 Page - STMicroelectronics |
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15 / 146 page ![]() Table 4. Interconnect of peripherals Interconnect source Interconnect destination Interconnect action TIMx TIMx Timer synchronization or chaining Y Y - ADCx DACx Conversion triggers Y Y - DMA Memory-to-memory transfer trigger Y Y - COMPx Comparator output blanking Y Y - COMPx TIM1, 2, 3 Timer input channel, trigger, break from analog signals comparison Y Y - LPTIMx Low-power timer triggered by analog signals comparison Y Y Y ADCx TIM1 Timer triggered by analog watchdog Y Y - RTC TIM16 Timer input channel from RTC events Y Y - LPTIMx Low-power timer triggered by RTC alarms or tampers Y Y Y All clock sources (internal and external) TIM16 Clock source used as input channel for RC measurement and trimming Y Y - CSS RAM (parity error) Flash memory (ECC error) COMPx PVD TIM1, 15, 16 Timer break Y Y - CPU (HardFault) TIM1 15, 16 Timer break Y - - GPIOs TIMx External trigger Y Y - LPTIMx External trigger Y Y Y ADCx DACx Conversion external trigger Y Y - 3.9 Reset and clock controller (RCC) 3.9.1 Reset mode During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce power consumption. In addition, when the reset source is internal, the built-in pull-up resistor on NRST pin is deactivated. 3.9.2 Clocks and startup The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features: • Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. STM32U073x8/B/C Functional overview DS14548 - Rev 2 page 15/146 |
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