STM32U073RCT3 datasheet(16/146 Pages) STMICROELECTRONICS

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•

Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration

•

Clock management: to reduce power consumption, the clock controller can stop the clock to the core,

individual peripherals or memory.

•

System clock source: two different sources can deliver SYSCLK system clock:

–

4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It can supply clock

to system PLL. The HSE can also be configured in bypass mode for an external clock.

–

16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can supply clock to

system PLL.

–

Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 12 frequencies form

100 kHz to 48 MHz. When a 32.768 kHz clock source is available in the system (LSE), the MSI

frequency can be automatically trimmed by hardware to reach an accuracy better than ± 0.25%. The

MSI can supply a PLL.

–

System PLL, which can be fed by HSE, HSI16 or MSI. It provides a system clock up to 56 MHz.

•

Auxiliary clock source: three ultra-low-power clock sources for the real-time clock (RTC), and the LCD

controller:

–

32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive capability modes.

The LSE can also be configured in bypass mode for using an external clock.

–

32 kHz low-speed internal RC oscillator (LSI) with ± 5% accuracy, also used to clock an independent

watchdog.

•

Peripheral clock sources: several peripherals (RNG, USARTs, I2Cs, LPTIMs, ADC) have their own clock

independent of the system clock.

•

Clock security system (CSS): in the event of HSE clock failure, the system clock is automatically

switched to HSI16 and, if enabled, a software interrupt is generated. LSE clock failure can also be detected

and generate an interrupt. The CSS feature can be enabled by software.

•

Clock output:

–

MCO (microcontroller clock output) provides one of the internal clocks for external use by the

application

–

LSCO (low speed clock output) provides LSI or LSE in all low-power modes (except in VBAT

operation).

Several prescalers enable the application to configure AHB and APB domain clock frequencies, 56 MHz at

maximum.

3.10

Clock recovery system (CRS)

The STM32U073x8/B/C devices embed a special block, which enables automatic trimming of the internal 48 MHz

oscillator, to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is

based on the external synchronization signal, which could be either derived from USB SOF signalization, from

LSE oscillator, from an external signal on CRS_SYNC pin, or generated by the user software. For faster lock-in

during startup, it is also possible to combine automatic trimming with manual trimming action.

3.11

General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without

pull-up or pull-down) or as peripheral alternate function (AF). Most of the GPIO pins are shared with special digital

or analog functions.

Through a specific sequence, this special function configuration of I/Os can be locked, such as to avoid spurious

writing to I/O control registers.

STM32U073x8/B/C

Functional overview

DS14548 - Rev 2

page 16/146

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