STM32U073RCT3 datasheet(95/146 Pages) STMICROELECTRONICS

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Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Resistive load

DAC output buffer ON

connected to VDDA

kΩ

Output Impedance

DAC output buffer OFF

9.6

11.7

13.8

kΩ

RBON

Output impedance sample and hold

mode, output buffer ON

VDD = 2.7 V

kΩ

VDD = 2.0 V

3.5

RBOFF

Output impedance sample and hold

mode, output buffer OFF

VDD = 2.7 V

16.5

kΩ

VDD = 2.0 V

18.0

Capacitive load

DAC output buffer ON

CSH

Sample and hold mode

0.1

µF

VDAC_OUT Voltage on DAC_OUT output

DAC output buffer ON

0.2

VREF+

- 0.2

DAC output buffer OFF

VREF+

tSETTLING

Settling time (full scale: for a 12-bit

code transition between the lowest

and the highest input codes when

DAC_OUT reaches final value

±0.5LSB, ±1 LSB, ±2 LSB, ±4 LSB,

±8 LSB)

Normal mode

DAC output buffer ON

CL ≤ 50 pF,

RL ≥ 5 kΩ

±0.5 LSB

1.7

µs

±1 LSB

1.6

2.9

±2 LSB

1.55

2.85

±4 LSB

1.48

2.8

±8 LSB

1.4

2.75

Normal mode DAC output buffer OFF, ±1LSB, CL

= 10 pF

2.5

tWAKEUP(1)

Wake-up time from off state (setting

the ENx bit in the DAC Control

Normal mode DAC output buffer ON

CL ≤ 50 pF, RL ≥ 5 kΩ

4.2

7.5

µs

Normal mode DAC output buffer OFF, CL ≤ 10 pF

PSRR

VDDA supply rejection ratio

Normal mode DAC output buffer ON

CL ≤ 50 pF, RL = 5 kΩ, DC

-80

-28

TW_to_W

Minimum time between two

consecutive writes into the

DAC_DORx register to guarantee a

correct DAC_OUT for a small

variation of the input code (1 LSB)

DAC_MCR:MODEx[2:0] = 000 or 001

CL ≤ 50 pF; RL ≥ 5 kΩ

µs

DAC_MCR:MODEx[2:0] = 010 or 011

CL ≤ 10 pF

1.4

tSAMP

Sampling time in sample and hold

mode (code transition between the

lowest input code and the highest

input code when DACOUT reaches

final value ±1LSB)

DAC_OUT pin connected

DAC output buffer ON,

CSH = 100 nF

0.7

3.5

DAC output buffer

OFF, CSH = 100 nF

10.5

DAC_OUT pin not

connected (internal

connection only)

DAC output buffer

OFF

3.5

µs

Ileak

Output leakage current

Sample and hold mode,

DAC_OUT pin connected

-(2)

CIint

Internal sample and hold capacitor

5.2

8.8

tTRIM

Middle code offset trim time

DAC output buffer ON

µs

Voffset

Middle code offset for 1 trim code

step

VREF+ = 3.6 V

1500

µV

VREF+ = 1.8 V

750

IDDA(DAC) DAC consumption from VDDA

DAC output buffer ON

No load, middle code

(0x800)

315

500

µA

No load, worst code

(0xF1C)

450

670

STM32U073x8/B/C

Electrical characteristics

DS14548 - Rev 2

page 95/146

STM32U073RCT3 Datasheet(PDF) 95 Page - STMicroelectronics

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