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STM32U073RCT6 Datasheet(PDF) 89 Page - STMicroelectronics |
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STM32U073RCT6 Datasheet(HTML) 89 Page - STMicroelectronics |
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89 / 146 page  Symbol Parameter Conditions(1) Min Typ Max Unit tADCVREG_STUP ADC voltage regulator start-up time - - - 20 µs tCONV Total conversion time (including sampling time) fADC = 35 MHz Resolution = 12 bits 0.40 - 4.95 µs Resolution = 12 bits ts + 12.5 cycles for successive approximation = 14 to 173 1/fADC tIDLE Laps of time allowed between two conversions without rearm - - - 100 µs IDDA(ADC) ADC consumption from VDDA fs = 2.5 MSps - 410 - µA fs = 1 MSps - 164 - fs = 10 kSps - 17 - IDDV(ADC) ADC consumption from VREF+ fs = 2.5 MSps - 65 - µA fs = 1 MSps - 26 - fs = 10 kSps - 0.26 - 1. I/O analog switch voltage booster must be enabled (BOOSTEN = 1 in the SYSCFG_CFGR1) when VDDA < 2.4 V and disabled when VDDA ≥ 2.4 V. 2. VREF+ is internally connected to VDDA on some packages. Refer to Section 4: Pinouts/ballouts, pin description, and alternate functions for further details. Table 71. Maximum ADC RAIN Resolution Sampling cycle at 35 MHz Sampling time at 35 MHz [ns] Max. RAIN (1)(2) (Ω) 12 bits 1.5(3) 43 50 3.5 100 680 7.5 214 2200 12.5 357 4700 19.5 557 8200 39.5 1129 15000 79.5 2271 33000 160.5 4586 50000 10 bits 1.5(3) 43 68 3.5 100 820 7.5 214 3300 12.5 357 5600 19.5 557 10000 39.5 1129 22000 79.5 2271 39000 160.5 4586 50000 8 bits 1.5(3) 43 82 3.5 100 1500 7.5 214 3900 12.5 357 6800 STM32U073x8/B/C Electrical characteristics DS14548 - Rev 2 page 89/146 |
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