STM32U073RCT6 datasheet(24/146 Pages) STMICROELECTRONICS

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The I2C-bus interface handles communication between the microcontroller and the serial I2C-bus. It controls all

I2C-bus-specific sequencing, protocol, arbitration and timing.

Features of the I2C peripheral:

•

I2C-bus specification and user manual rev. 5 compatibility:

–

Slave and master modes, multimaster capability

–

Standard-mode (Sm), with a bitrate up to 100 kbit/s

–

Fast-mode (Fm), with a bitrate up to 400 kbit/s

–

Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and extra output drive I/Os

–

7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

–

Programmable setup and hold times

–

Clock stretching

•

Independent clock: a choice of independent clock sources allowing the I2C communication speed to be

independent of the PCLK reprogramming

•

Wake-up from Stop mode on address match

•

Programmable analog and digital noise filters

•

1-byte buffer with DMA capability

Table 8. I2C implementation

I2C features

I2C1

I2C2

I2C3

I2C4

Standard mode (up to

100 kbit/s)

Fast mode (up to

400 kbit/s)

Fast mode Plus (up to

1 Mbit/s) with extra

output drive I/Os

Programmable analog

and digital noise filters

SMBus/PMBus

hardware support

Independent clock

Wakeup from Stop

mode on address

match

3.27

Universal synchronous/asynchronous receiver transmitter (USART/UART)

The devices embed universal synchronous/asynchronous receivers/transmitters that communicate at speeds of

up to 8 Mbit/s.

They provide hardware management of the CTS, RTS and RS485 DE signals, multiprocessor communication

mode, synchronous SPI master/slave communication and single-wire half-duplex communication mode. Some

can also support smartcard communication (ISO 7816), IrDA SIR ENDEC, LIN master/slave capability and auto

baud rate feature, and have a clock domain independent of the CPU clock, which allows them to wake up the

MCU from Stop mode. The wake-up events from Stop mode are programmable and can be:

•

Start bit detection

•

Any received data frame

•

A specific programmed data frame

All USART interfaces can be served by the DMA controller.

Table 9. USART implementation

X: supported

STM32U073x8/B/C

Functional overview

DS14548 - Rev 2

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