8.2.2.3 Differential to Single-Ended Output Conversion

Figure 8-3 shows an example of a TLV900x-based signal conversion and filter circuit for systems using single-

ended input ADCs to convert the analog output voltage into digital. For R1 = R3 and R2 = R4, the output voltage

equals (R2 / R1) × (VOUTP – VOUTN) + VREF. Tailor the bandwidth of this filter stage to the bandwidth requirement

of the system and use NP0-type capacitors for best performance. For most applications, R1 = R2 = R3 = R4 =

3.3 kΩ and C1 = C2 = 330 pF yields good performance.

VDD1

GND1

INP

INN

AMC1301

VDD2

OUTP

OUTN

GND2

+

–

R4

R3

R1

R2

V

REF

ADC

To MCU

C1

C2

TLV9001

Figure 8-3. Connecting the AMC1301 Output to a Single-Ended Input ADC

For more information on the general procedure to design the filtering and driving stages of SAR ADCs, see

the 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data

Acquisition Block (DAQ) Optimized for Lowest Power reference guides, available for download at www.ti.com.

8.2.3 Application Curve

One important aspect of power-stage design is the effective detection of an overcurrent condition to protect the

switching devices and passive components from damage. To power off the system quickly in the event of an

overcurrent condition, a low delay caused by the isolated amplifier is required. Figure 8-4 shows the typical

full-scale step response of the AMC1301.

VIN

VOUTP

VOUTN

Figure 8-4. Step Response of the AMC1301

AMC1301

SBAS667G – APRIL 2016 – REVISED APRIL 2023

www.ti.com

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