CC430F6137IRGCT.B datasheet(13/133 Pages) TI2

13 / 133 page

CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125

CC430F5137, CC430F5135, CC430F5133

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SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018

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Terminal Configuration and Functions

Table 4-1. CC430F613x and CC430F612x Terminal Functions (continued)

TERMINAL

I/O(1)

DESCRIPTION

NAME

NO.

PJ.1/ TDI/ TCLK

I/O

General-purpose digital I/O

Test data input or test clock input

PJ.2/ TMS

I/O

General-purpose digital I/O

Test mode select

PJ.3/ TCK

I/O

General-purpose digital I/O

Test clock

TEST/ SBWTCK

Test mode pin – select digital I/O on JTAG pins

Spy-Bi-Wire input clock

RST/NMI/ SBWTDIO

I/O

Reset input active low

Nonmaskable interrupt input

Spy-Bi-Wire data input/output

DVCC

Digital power supply

AVSS

Analog ground supply for ADC12

P5.1/ XOUT

I/O

General-purpose digital I/O

Output terminal of crystal oscillator XT1

P5.0/ XIN

I/O

General-purpose digital I/O

Input terminal for crystal oscillator XT1

AVCC

Analog power supply

P2.7/ PM_ADC12CLK/

PM_DMAE0/ CB7 (/A7)

I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: ADC12CLK output

Default mapping: DMA external trigger input

Comparator_B input CB7

Analog input A7 – 12-bit ADC (CC430F613x only)

P2.6/ PM_ACLK/ CB6 (/A6)

I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: ACLK output

Comparator_B input CB6

Analog input A6 – 12-bit ADC (CC430F613x only)

P2.5/ PM_SVMOUT/ CB5

(/A5/ VREF+/ VeREF+)

I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: SVM output

Comparator_B input CB5

Analog input A5 – 12-bit ADC (CC430F613x only)

Output of reference voltage to the ADC (CC430F613x only)

Input for an external reference voltage to the ADC (CC430F613x only)

P2.4/ PM_RTCCLK/ CB4

(/A4/ VREF-/ VeREF-)

I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: RTCCLK output

Comparator_B input CB4

Analog input A4 – 12-bit ADC (CC430F613x only)

Negative terminal for the ADC reference voltage for both sources, the internal reference

voltage, or an external applied reference voltage (CC430F613x only)

P2.3/ PM_TA1CCR2A/ CB3 (/A3)

I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: TA1 CCR2 compare output or capture input

Comparator_B input CB3

Analog input A3 – 12-bit ADC (CC430F613x only)

P2.2/ PM_TA1CCR1A/ CB2 (/A2)

I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: TA1 CCR1 compare output or capture input

Comparator_B input CB2

Analog input A2 – 12-bit ADC (CC430F613x only)

P2.1/ PM_TA1CCR0A/ CB1 (/A1)

I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: TA1 CCR0 compare output or capture input

Comparator_B input CB1

Analog input A1 – 12-bit ADC (CC430F613x only)

P2.0/ PM_CBOUT1/ PM_TA1CLK/

CB0 (/A0)

I/O

General-purpose digital I/O with port interrupt and mappable secondary function

Default mapping: Comparator_B output

Default mapping: TA1 clock input

Comparator_B input CB0

Analog input A0 – 12-bit ADC (CC430F613x only)

VSS, Exposed die attach pad

Ground supply

CAUTION: The exposed die attach pad must be connected to a solid ground plane as

this is the ground connection for the chip.

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