CC430F6137IRGCT.B datasheet(32/133 Pages) TI2

32 / 133 page

CC430F6137, CC430F6135, CC430F6127, CC430F6126, CC430F6125

CC430F5137, CC430F5135, CC430F5133

SLAS554I – MAY 2009 – REVISED SEPTEMBER 2018

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Specifications

5.27 USCI (UART Mode) Clock Frequency

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

fUSCI

USCI input clock frequency

Internal: SMCLK or ACLK,

External: UCLK,

Duty cycle = 50% ±10%

fSYSTEM

MHz

fBITCLK BITCLK clock frequency (equals baud rate in MBaud)

MHz

(1)

Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized, their duration should exceed the maximum specification of the deglitch time.

5.28 USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

VCC

MIN

MAX

UNIT

tτ

UART receive deglitch time(1)

2.2 V

600

3 V

600

5.29 USCI (SPI Master Mode) Clock Frequency

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

fUSCI

USCI input clock frequency

Internal: SMCLK or ACLK,

Duty cycle = 50% ±10%

fSYSTEM

MHz

(1)

fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave))

For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.

(2)

Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

in Figure 5-14 and Figure 5-15.

(3)

Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-

14 and Figure 5-15.

5.30 USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1) (see Figure 5-14

and Figure 5-15)

PARAMETER

TEST CONDITIONS

PMMCOREVx

VCC

MIN

MAX

UNIT

tSU,MI

SOMI input data setup time

1.8 V

3 V

2.4 V

3 V

tHD,MI

SOMI input data hold time

1.8 V

3 V

2.4 V

3 V

tVALID,MO

SIMO output data valid time(2)

UCLK edge to SIMO valid,

CL = 20 pF

1.8 V

3 V

2.4 V

3 V

tHD,MO

SIMO output data hold time(3)

CL = 20 pF

1.8 V

–10

3 V

–8

2.4 V

–10

3 V

–8

CC430F6137IRGCT.B Datasheet(PDF) 32 Page - Texas Instruments

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