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STM32WL33C8 Datasheet(PDF) 6 Page - STMicroelectronics |
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STM32WL33C8 Datasheet(HTML) 6 Page - STMicroelectronics |
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6 / 91 page  2 Description The STM32WL33xx is a high performance ultra-low power wireless application processor, intended for RF wireless applications in the sub-1 GHz band. It is designed to operate in both the license-free ISM and SRD frequency bands such as 433, 868, and 915 MHz. It adopts a single-core architecture embedding an Arm® 32-bit Cortex®-M0+ CPU that can operate up to 64 MHz. It integrates high-speed and flexible memory types: up to 256 Kbyte flash memory, and up to 32 Kbyte RAM, one- time programmable (OTP) memory area of 1 Kbyte. The STM32WL33xx embeds a wide set of peripherals, including a 20-pin (16 segments + 4 commons) LCD driver, 12-bit, 8 channel ADC, analog comparator, DAC, LC sensor controller, RTC, IWDG, general purpose timers, AES-128, RNG, CRC, communication interfaces such as USART, SPI, and I2C. Moreover, the security features enable secure boot with USART/SWD block (write protection) and sensitive information storage in flash (read-out protection). Direct data transfer between memory and peripherals and from memory-to-memory is supported by seven DMA channels with fully-flexible channel mapping by the DMAMUX peripheral. It can be configured to support standalone or network processor applications. In the first configuration, the STM32WL33xx operates as single device in the application for managing both the application code and proprietary sub-1 GHz protocol stacks. It operates in the -40 to +105 °C temperature range from a 1.7 V to 3.6 V power supply. A comprehensive set of power-saving modes enables the design of low-power applications. The integrated highly efficient SMPS step-down converter together with the state transition speed between low- power and active states minimize in every condition the average current consumption enabling the STM32WL33xx to be the wireless application processor most suited for battery-operated applications. The STM32WL33xx comes in different package versions supporting up to 32 I/Os for the VFQFPN48 package and 17 I/Os for the VFQFPN32 package. Figure 1. Block diagram SRAM0 CTRL SRAM0 (16 Kbytes) 32 kHz XO 32 kHz RC 64 MHz RC RCC GPIOA GPIOB CRC RNG AES PWRCTRL POR/ BOR 48 MHz XO RF_SUBG (ana) MR_SUBG (dig) wakeup PVD CLKDETR LDO /SMPS LPAWUR wakeup Radio (dig) LPAWUR (ana) Flash interface Flash (256 Kbytes /8 Kbytes) CM0+ SW / JTAG MPU NVIC DMA MUX DMA 8ch AHB Up Temp. sensor BM 4S/1M VDD12o VDD12I VDD12o_ram1 SRAM1 CTRL SRAM1 (16 Kbytes) AHB down APB bridge APB bridge APB bridge BUSMATRIX 3S/7M VDD VDD power domain VDD12o power domain VDD12I power domain VDD12o_ram1 supply APB0 APB1 STM32WL33xx Description DS14221 - Rev 5 page 6/91 |
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