STM32WL33C8 datasheet(24/91 Pages) STMICROELECTRONICS

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Interrupt/DMA generation on the following events:

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update: counter overflow

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input capture

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output comparison

–

break input (interrupt request)

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Synchronization circuit to trigger the DAC

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The counter can be frozen in debug mode.

3.17

Independent watchdog (IWDG)

TheSTM32WL33 integrates an embedded watchdog peripheral which offers a combination of high safety level,

timing accuracy and flexibility of use. The independent watchdog peripheral serves to detect and resolve

malfunctions due to software failure, and to trigger system reset when the counter reaches a given timeout value.

The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI) and thus stays active

even if the main clock fails.

The IWDG is best suited to applications which require the watchdog to run as a totally independent process

outside the main application but have lower timing accuracy constraints. The counter can be frozen in debug

mode.

3.18

Real-time clock (RTC)

The STM32WL33xx integrates a real-time clock (RTC). It is an independent BCD timer/counter. The RTC

provides a time of day/clock/calendar with programmable alarm interrupt. RTC includes also a periodic

programmable wake-up flag with interrupt capability. The RTC provides an automatic wake-up to manage all low

power modes.

Two 32-bit registers contain seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day of

month), month, and year, expressed in binary coded decimal format (BCD). The sub-second value is also

available in binary format. Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed

automatically. Daylight saving time compensation can also be performed. Additional 32-bit registers contain the

programmable alarm sub seconds, seconds, minutes, hours, day, and date.

One anti-tamper detection pin with programmable filter is available. A timestamp feature can be used to save the

calendar content. This function can be triggered by an event on the timestamp pin, by a tamper event, or by a

switch to Deepstop mode.

A digital calibration circuit is available to compensate for quartz crystal inaccuracy. After power-on reset, all RTC

registers are protected against possible parasitic write accesses. As long as the supply voltage remains in the

operating range, the RTC never stops, regardless of the device status (Run mode, low power mode or under

system reset).

The RTC contains 5 backup registers which are supplied through a switch that takes power either from the

VDD12I supply (when present) or from the VDD12O pin.

The backup registers are 32-bit registers used to store 20 bytes of user application data when VDD12I power is

not present. They are not reset by a system or power reset, or when the device wakes up from Deepstop mode.

All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt and wakeup the device

from the low-power modes. The counter can be frozen in debug mode.

3.19

Inter-integrated circuit interface (I2C)

The I2C (inter-integrated circuit) bus interface handles communications between the microcontroller and the serial

I2C bus. It provides multi master capability, and controls all I2C bus-specific sequencing, protocol, arbitration, and

timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).

It is also SMBus (system management bus) and PMBus (power management bus) compatible.

DMA can be used to reduce CPU overload. The counter can be frozen in debug mode.

STM32WL33xx

Functional overview

DS14221 - Rev 5

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