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STM32WL33C8 Datasheet(PDF) 25 Page - STMicroelectronics |
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STM32WL33C8 Datasheet(HTML) 25 Page - STMicroelectronics |
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25 / 91 page  3.20 Universal synchronous/asynchronous receiver transmitter (USART) The STM32WL33xx embeds a universal synchronous asynchronous receiver transmitter (USART) that offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The USART offers a very wide range of baud rates using a fractional baud rate generator. It supports synchronous one-way communication and half-duplex single wire communication. It also supports the LIN (local interconnection network), SmartCard Protocol and IrDA (infrared data association) SIR ENDEC specifications, and modem operations (CTS/RTS). It also supports multiprocessor communications. High speed data communication is possible by using the DMA (direct memory access) for multibuffer configuration. The USART main features are: • Full-duplex asynchronous communication • NRZ standard format (mark/space) • Configurable oversampling method by 16 or 8 to give flexibility between speed and clock tolerance • Baud rate generator systems • Two internal FIFOs for transmit and receive data, that can be enabled/disabled by software. FIFOs come with status flags for FIFOs states. • A common programmable transmit and receive baud rate of up to 2Mbit/s with the clock frequency at 16 MHz and oversampling is by 8 • Dual clock domain with a dedicated kernel clock allowing baud rate programming independent from the PCLK reprogramming. • Auto baud rate detection • Programmable data word length (7 or 8 or 9 bits) • Programmable data order with MSB-first or LSB-first shifting • Configurable stop bits (1 or 2 stop bits) • Synchronous master/slave mode and clock output/input for synchronous communications • SPI slave transmission underrun error flag Single-wire half-duplex communications • Continuous communications using DMA • Received/transmitted bytes are buffered in reserved SRAM using centralized DMA • Separate enable bits for transmitter and receiver • Separate signal polarity control for transmission and reception • Swappable Tx/Rx pin configuration • Hardware flow control for modem and RS-485 transceiver • Communication control/error detection flags • Parity control: – Transmits parity bit – Checks parity of received data byte • Interrupt sources with flags • Multiprocessor communications • Wake up from mute mode (by idle line detection or address mark detection) STM32WL33xx Functional overview DS14221 - Rev 5 page 25/91 |
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