L9001 datasheet(18/38 Pages) STMICROELECTRONICS

18 / 38 page

Power supply

L9001

18/38

DS12089 Rev 2

5.4

ADCLDO Regulator

ADCLDO is a LDO power supply with integrated FET. The input voltage is VS pin; the output

voltage is VADC which can be selected as either 3.3 V or 5.0 V as described in Section 5.1.

5.5

Power up and power down sequences

As soon as the battery level on VS in greater than 5.5 V and the pin WAKE reaches a value

greater than WAKE_Hth (see Table 12) for a minimum time of WPH, the internal regulators

are activated.

A dedicated design approach is used to mitigate emissions and soft start control is used to

define the start-up behavior.

When internal regulators are ready, at first VDD1 regulator is activated with soft start

functionality. When the under-voltage threshold is reached, the other regulators (VDD2 and

ADCLDO) are activated with soft start functionality. In case the VDD1 regulator is not used,

the VDD2 and ADCLDO regulators will start right after internal regulators are ready.

In the power down sequence, as soon as WAKE goes below WAKE_Lth (see Table 12) for a

minimum time of WPL, the internal regulators and all output pins are deactivated.

ESR_Cout2

Eq. series resistance

for Cout2

Application info

mΩ

Cin1_vdd2

Bypass capacitor at

VR1 pin

Application info

100

Cin2_vdd2

4.7

μF

1. For further load/line transient details, please refer to AN5163.

Table 10. VDD2 regulator parameters (continued)

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

Table 11. ADCLDO regulator parameters

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

VADC

Output voltage

CONF1 LOW

3.23

3.3

3.37

VADC

CONF1 HIGH

4.9

5.1

IloadADC

Output current

Application info

100

dVSRADC_ac

Line transient response

Not tested, guaranteed by design,

SR < 1 V/μs

-5

dVLRADC_ac

Load transient response Not tested, guaranteed by design

-5

IlimADC

Current limitation

100

RDSonADC

High side RDSon

-SSADC

Soft start control

CONF1 LOW (20%-80% of VADC)

V/ms

CONF1 HIGH (20%-80% of VADC)

V/ms

Cadc

Capacitor at VADC

Application info

0.7

μF

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