L9001 datasheet(28/38 Pages) STMICROELECTRONICS

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Operation modes

L9001

28/38

DS12089 Rev 2

8.2.4

LOW POWER mode

Low power mode corresponds to a state where the system needs to decrease the overall

power consumption with a reduced level of functionality. In this state, ADCLDO is switched

off, regulators VDD1 and VDD2 are working in bypass mode and Watchdog, over

temperature, regulators over & under voltage are all disabled.

The state can be entered by ACTIVE state by rising STBY pin. Depending on the active

VDD regulators (i.e. the regulators which have not been disabled in the application), the low

power mode is managed in a different way.

When only VDD1 regulator is enabled and the STBY pin is asserted high, the device goes in

LOW POWER mode if VR1 current is lower than ICMP1_l. In this case only the bypass LDO

drives the wanted output voltage while the switch mode operation is deactivated. When VR1

current turns higher than ICMP1_h, the device goes back to ACTIVE mode.

When only VDD2 regulator is enabled and the STBY pin is asserted high, the device goes in

LOW POWER mode if VR2 current is lower than ICMP2_l. In this case only the bypass LDO

drives the wanted output voltage. When VR2 current turns higher than ICMP2_h, the device

goes back to ACTIVE mode.

When both regulators are enabled and the STBY pin is asserted high and the total overall

current generated by VDD1 regulator is lower than ICMP1_l, the device goes in LOW

POWER mode and only the bypass LDOs drive the output voltages while the switch mode

operation (or linear mode, depending on the configuration) is deactivated. When the total

overall current turns higher than ICMP1_h, the device goes back to ACTIVE mode.

For further details on transitions from and to low power mode please refer to AN5163.

8.2.5

SAFE mode

SAFE mode corresponds to a state that is entered automatically when a fail-safe triggering

condition is generated in ACTIVE state. These failure conditions are four: over temperature

shutdown, VS overvoltage, VS undervoltage, and charge pump undervoltage. When in

SAFE mode, all output regulators and watchdog are switched off, monitoring and charge

pump are still active. Exit from SAFE state occurs only if Failure condition disappears.

8.2.6

LATCH mode

LATCH mode corresponds to a state that is entered automatically when the system has

persistent failures which are blocking the functionality and so it must be stopped or

restarted. Thus the only way out of LATCH state is going to OFF state and then again in

ACTIVE, otherwise the system will remain in LATCH state indefinitely.

In LATCH state all output regulators and WD are switched off, monitoring and charge pump

are also switched off, and WDO is low.

In particular, the failures that can trigger LATCH state are: over temperature shutdown

(OTSD), charge pump undervoltage (CP_UV) and watchdog fail.

The IC has two separate failure counters:



WD_FC which counts fails on watchdog;



FC which counts fails on OTSD and CP_UV.

Each time a failure is detected, the correspondent failure counter is incremented; LATCH

mode occurs when either the FC failure counter or the WD_FC has reached a threshold of 4

failures.

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