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VNF9Q20F Datasheet(PDF) 30 Page - STMicroelectronics |
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VNF9Q20F Datasheet(HTML) 30 Page - STMicroelectronics |
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30 / 111 page  Address Name Description Access Content 10h SPI mode Different modes of the SPI (see SPI mode) Read only A1H 11h WD type 1 Indicates the type of watchdog used in the product Read only 46H 13h WD bit position 1 Indicates the address of the register containing the WD toggle bit Read only 40H 14h WD bit position 2 Indicates the position of the WD toggle bit Read only C1H Not used area 20h SPI CPHA Indicates the polarity and phase of the SPI interface Read only 55H 3Eh GSB options Options of GSB byte (standard GSB definition) Read only 00H 3Fh Advanced op. code 4.3.4 SPI modes By reading out the <SPI Mode> register general information of SPI usage of the device application registers can be read. Table 27. SPI Mode Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Content BR DL2 DL1 DL0 SPI8 0 S1 S0 A1H SPI Burst Read Table 28. SPI Burst Read Bit 7 Description 0 BR disabled 1 BR enabled The Burst Read is implemented in this product so this bit is enabled. SPI Data Length The SPI Data Length value indicates the length of the SCK count monitor which is running for all the accesses to the Device Application Registers. In case a communication frame with an SCK count is not equal to the reported one, the device will lead to a SPI Error and the data will be rejected. The Frame Length is specified on 3 bits in the SPI Mode register located in the ROM part. The 24-bit SPI communication is implemented in this product, so these bits are ‘010’. Table 29. SPI Data Length Bit 6 Bit 5 Bit 4 Description DL2 DL1 DL0 0 0 0 Invalid 0 0 1 16 bit SPI 0 1 0 24 bit SPI ... ... 1 1 1 64 bit SPI VNF9Q20F SPI functional description DS13909 - Rev 8 page 30/111 |
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