SPC563M60L7 datasheet(66/128 Pages) STMICROELECTRONICS

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Pinout and signal description

SPC563M64x, SPC563M60x

66/128

DocID14642 Rev 12

Table 7 gives the power/ground segmentation of the SPC563Mx MCU. Each segment

provides the power and ground for the given set of I/O pins, and can be powered by any of

the allowed voltages regardless of the power on the other segments.

NMI

SIU – External

Interrupts

Non-Maskable Interrupt

GPIO[n]

SIU – GPIO

Configurable general purpose I/O pins. Each GPIO input and

output is separately controlled by an 8-bit input (GPDI) or

output (GPDO) register. Additionally, each GPIO pins is

configured using a dedicated SIU_PCR register.

The GPIO pins are generally multiplexed with other I/O pin

functions.

RESET

SIU – Reset

The RESET pin is an active low input. The RESET pin is

asserted by an external device during a power-on or external

reset. The internal reset signal asserts only if the RESET pin

asserts for 10 clock cycles. Assertion of the RESET pin while

the device is in reset causes the reset cycle to start over.

The RESET pin has a glitch detector which detects spikes

greater than two clock cycles in duration that fall below the

switch point of the input buffer logic of the VDDEH input pins.

The switch point lies between the maximum VIL and minimum

VIH specifications for the VDDEH input pins.

RSTOUT

SIU – Reset

The RSTOUT pin is an active low output that uses a push/pull

configuration. The RSTOUT pin is driven to the low state by the

MCU for all internal and external reset sources. There is a

delay between initiation of the reset and the assertion of the

RSTOUT pin.

Table 6. Signal details (continued)

Signal

Module or Function

Description

Table 7. SPC563Mx Power/Ground Segmentation

Power

Segment

144-LQFP Pin

Number

176-LQFP Pin

Number

Voltage

Range(1)

I/O Pins Powered

by Segment

VDDA0

5.0 V

AN[0:7], AN[9], AN[11], AN[16:18],

AN[21:25], AN[27:28], AN[30:37], AN38,

AN39, VRL, REFBYPC,

VRH

VDDEH1 (a, b)

24, 34

31, 41

3.3 V – 5.0 V

PCKCFG[2],

eTPU_A[0:31],

eMIOS[0:2]

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