SPC563M60L7 datasheet(86/128 Pages) STMICROELECTRONICS

86 / 128 page

Electrical characteristics

SPC563M64x, SPC563M60x

86/128

DocID14642 Rev 12

RPUPD5K

Weak Pull-Up/Down

Resistance(26)

5 k

 Option

5 V ± 5%

supply

1.4

—

7.5



TA (TL to TH)SR

—

Operating temperature

range - ambient

(packaged)

—–40.0

—

125.0

C

—SR

—

Slew rate on power

supply pins

——

—

V/ms

VDDE must be lower than VRC33, otherwise there is additional leakage on pins supplied by VDDE.

These specifications apply when VRC33 is supplied externally, after disabling the internal regulator (VDDREG = 0).

ADC is functional with 4 V

V

DDA  4.75 V but with derated accuracy. This means the ADC will continue to function at full

speed with no bad behavior, but the accuracy will be degraded.

Internal structures hold the input voltage less than VDDA + 1.0 V on all pads powered by VDDA supplies, if the maximum

injection current specification is met (3 mA for all pins) and VDDA is within the operating voltage specifications.

The VDDF supply is connected to VDD in the package substrate. This specification applies to calibration package devices

only.

VFLASH is only available in the calibration package.

Regulator is functional, with derated performance, with supply voltage down to 4.0 V.

Multi-voltage pads (type pad_multv_hv) must be supplied with a power supply between 4.75 V and 5.25 V.

The slew rate (SRC) setting must be 0b11 when in low-swing mode.

10. While in low-swing mode there are no restrictions in transitioning to high-swing mode.

11. Pin in low-swing mode can accept a 5 V input.

12. Pin in low-swing mode can accept a 5 V input.

13. Characterization based capability:



IOH_S = {6, 11.6} mA and IOL_S = {9.2, 17.7} mA for {slow, medium} I/O with VDDEH=4.5 V;



IOH_S = {2.8, 5.4} mA and IOL_S = {4.2, 8.1} mA for {slow, medium} I/O with VDDEH=3.0 V

14. Characterization based capability:



IOH_F = {12, 20, 30, 40} mA and IOL_F = {24, 40, 50, 65} mA for {00, 01,10, 11} drive mode with VDDE=3.0 V;



IOH_F = {7, 13, 18, 25} mA and IOL_F = {18, 30, 35, 50} mA for {00, 01, 10, 11} drive mode with VDDE=2.25 V;



IOH_F = {3, 7, 10, 15} mA and IOL_F = {12, 20, 27, 35} mA for {00, 01, 10, 11} drive mode with VDDE=1.62 V

15. All VOL/VOH values 100 % tested with ± 2 mA load.

16. Run mode as follows:



System clock = 40/60/80 MHz + FM 2 %



Code executed from Flash memory



ADC0 at 16 MHz with DMA enabled



ADC1 at 8 MHz



eMIOS pads toggle in PWM mode with a rate between 100 kHz and 500 kHz



eTPU pads toggle in PWM mode with a rate between 10 kHz and 500 kHz



CAN configured for a bit rate of 500 kHz



DSPI configured in master mode with a bit rate of 2 MHz



eSCI transmission configured with a bit rate of 100 kHz

17. Bypass mode, system clock at 1 MHz (using system clock divider), PLL shut down, CPU running simple executive code,

4 x ADC conversion every 10 ms, 2 × PWM channels at 1 kHz, all other modules stopped.

18. Bypass mode, system clock at 1 MHz (using system clock divider), CPU stopped, PIT running, all other modules stopped.

19. When using the internal regulator only, a bypass capacitor should be connected to this pin. External circuits should not be

20. Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a

particular I/O segment, and the voltage of the I/O segment. See Table 24 for values to calculate power dissipation for

specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for

each pin on the segment.

21. Absolute value of current, measured at VIL and VIH.

Table 23. DC electrical specifications (continued)

Symbol

Parameter

Conditions

Value

Unit

Min

Typ

Max

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