L99MH98 datasheet(52/147 Pages) STMICROELECTRONICS

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6.4.3

Clear on read scenario

When a clear on read communication must be performed the following steps must be considered:

•

Frame n

–

SDI:

◦

Bit 23 = 0 (read command on the OpCode)

◦

Bit 22 = Not used

◦

Bits 21 to 16 = Address of the register to read

◦

Bits 15 to 1 = Set to 0 the bits “not to clear”, set to 1 the bits “to clear”

◦

Bit 0 = Parity bit

–

SDO:

◦

Bit 23 = 0 (no SPI error or RESET in the previous access)

◦

Bit 22 = GSBN bit (1 = No fault)

◦

Bits 21 to 16 = Address of the register selected in the previous frame (n-1)

◦

Bits 15 to 1 = Data value of the register selected in the previous frame (n-1)

◦

Bit 0 = Parity bit

•

Frame n+1

–

SDI:

◦

Bit 23 = 0 or 1 (read or write command on the OpCode)

◦

Bit 22 = Not used

◦

Bits 21 to 16 = Address of the register to read or write

◦

Bits 15 to 1 = Data to write into the chosen register

◦

Bit 0 = Parity bit

–

SDO:

◦

Bit 23 = 0 (no SPI error or RESET in the previous access)

◦

Bit 22 = GSBN bit (1 = No fault)

◦

Bits 21 to 16 = Address of the register selected in the previous frame (n)

◦

Bits 15 to 1 = Data value of the register selected in the previous frame (n) with the bits cleared

◦

Bit 0 = Parity bit

Figure 35. Clear on Read scenario

Frame n

0 = Read

Address of the register

to read reg1

Clear on read register bit15, bit14 and bit1 are set to ‘1’

Data field: bit15 is set to ‘0’  not to clear,

while bit14 and bit1 are set to ‘1’  to clear

Frame n+1

After frame n cs rising edge, the clear on read is executed to bit 14 and bit1 as commanded



now the register value is with only bit15 set to ‘1’

Data value of reg1 (selected by SDI during previous

frame (n)) saved at frame n+1 cs falling

L99MH98

Serial peripheral interface (SPI)

DS14611 - Rev 3

page 52/147

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