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LM5145 Datasheet(PDF) 10 Page - Texas Instruments |
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LM5145 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 73 page  6.5 Electrical Characteristics (continued) Typical values are at TJ = 25°C. Minimum and maximum limits apply at TJ = –40°C to 150°C. VIN = 12V, unless otherwise stated. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VBIAS-ON VBIAS1/VOUT1 rising 4.1 4.3 4.5 V VBIAS-HYST Bias hysteresis voltage 130 mV REFERENCE VOLTAGE (FB1, FB2) VREF1 Regulated FB voltage 792 800 808 mV PRECISION ENABLE (EN1, EN2) VSDN1/2 Shutdown-to-standby threshold VEN1/2 rising 0.6 V VEN1/2-HIGH Enable voltage rising threshold VEN1/2 rising, switching enabled 0.95 1.0 1.05 V VEN1/2-HYS Enable hysteresis voltage 50 mV IEN1/2-HYS Enable hysteresis current VEN1/2 = 1.1V –12 –10 –8 µA OUTPUT VOLTAGE (VOUT1/BIAS1, VOUT2) VOUT1/2-3.3V 3.3V fixed output setpoint RFB1/2 = 7.5kΩ, 4V ≤ VVIN ≤ 42V 3.267 3.3 3.33 V VOUT1/2-5V 5V fixed output setpoint RFB1/2 = 24.9kΩ 4.95 5 5.05 V VOUT1/2-12V 12V fixed output setpoint RFB1/2 = 48.7kΩ, 13V ≤ VVIN ≤ 42V 11.82 12 12.18 V ERROR AMPLIFIER (COMP1, COMP2) gm1/2 EA transconductance ΔVFB1/2 ± 50mV 400 600 µS VCOMP1/2-CLAMP COMP clamp voltage VFB1/2 = 0V 1.75 V ICOMP1/2-SRC EA source current VCOMP1/2 = 1V, VFB1/2 = 0.6V 120 µA ICOMP1/2-SINK EA sink current VCOMP1/2 = 1V, VFB1/2 = 1V 120 µA VDRIVER1/2-DISABLE COMP threshold voltage below which the driver is disabled 100 mV POWER GOOD (PG1, PG2) VPG1/2-OV PG1/2 overvoltage Rising threshold 103 105 107 % VPG1/2-OV-HYST PG1/2 OV hysteresis 1 % VPG1/2-UV PG1/2 undervoltage Falling threshold 93 95 97 % VPG1-UV-HYST PG1/2 UV hysteresis 1 % t-PG1/2-DEGLITCH(R) PG1/2 deglitch rising 1.4 2 2.6 ms t-PG1/2-DEGLITCH(F) PG1/2 deglitch falling 60 90 120 µs RPG1/2(on) PG1/2 on resistance Open drain, IPG1/2 = 250µA 100 250 Ω SWITCHING FREQUENCY (RT) FSW1 Switching frequency 1 RRT = 100kΩ to AGND 230 kHz FSW2 Switching frequency 2 RRT = 10kΩ to AGND 1.98 2.2 2.42 MHz FSW3 Switching frequency 3 RRT = 230kΩ to AGND 100 kHz SLOPE1 Internal slope compensation 1 RRT = 10kΩ to AGND 500 mV/µs SLOPE2 Internal slope compensation 2 RRT = 100kΩ to AGND 42 mV/µs tON(min) PWM minimum on-time 22 35 ns tOFF(min) PWM minimum off-time Measured at nominal frequency, before the frequency folds back to achieve 100% duty cycle 45 ns DMAX Maximum duty cycle 100 % SYNCHRONIZATION OUTPUT (SYNCOUT) VSYNCOUT-HO SYNCOUT high-state voltage ISYNCOUT = –4mA 2 V VSYNCOUT-LO SYNCOUT low-state voltage ISYNCOUT = 4mA 0.8 V tSYNCOUT1 Delay from HO1 rising edge to SYNCOUT rising edge VPFM/SYNC = 0V, TS = 1/FSW, FSW set by RRT = 230kΩ 2.5 µs tSYNCOUT2 Delay from HO1 rising edge to SYNCOUT falling edge VPFM/SYNC = 0V, TS = 1/FSW, FSW set by RRT = 230kΩ 7.5 µs PULSE FREQUENCY MODULATION and SYNCHRONIZATION INPUT (PFM/SYNC) VPFM-LO PFM detection threshold low 0.8 V VPFM-HI PFM detection threshold high 1.2 V LM25137 SNVSCU4 – OCTOBER 2025 www.ti.com 10 Submit Document Feedback Copyright © 2025 Texas Instruments Incorporated Product Folder Links: LM25137 |
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