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4. Follow any layout considerations of the MOSFETs as recommended by the MOSFET manufacturer,

including pad geometry and solder paste stencil design.

5. The SW pin connects to the switch node of the power conversion stage and acts as the return path for the

high-side gate driver. The parasitic inductance inherent to loop 1 in Figure 7-22 and the output capacitance

(COSS) of both power MOSFETs form a resonant circuit that induces high frequency (greater than 50MHz)

ringing at the SW node. The voltage peak of this ringing, if not controlled, can be significantly higher than

the input voltage. Make sure that the peak ringing amplitude does not exceed the absolute maximum rating

limit for the SW pin. In many cases, a series resistor and capacitor snubber network connected from the SW

node to GND damps the ringing and decreases the peak amplitude. Provide provisions for snubber network

components in the PCB layout. If testing reveals that the ringing amplitude at the SW pin is excessive, then

include snubber components as needed.

7.4.1.2 Gate Drive Layout

The LM25139 high-side and low-side gate drivers incorporate short propagation delays, adaptive dead time

control, and low-impedance output stages capable of delivering large peak currents with very fast rise and

fall times to facilitate rapid turn-on and turn-off transitions of the power MOSFETs. Very high di/dt can cause

unacceptable ringing if the trace lengths and impedances are not well controlled.

Minimization of stray or parasitic gate loop inductance is key to optimizing gate drive switching performance,

whether series gate inductance resonates with MOSFET gate capacitance or common source inductance

(common to gate and power loops) provides a negative feedback component opposing the gate drive command,

thereby increasing MOSFET switching times. The following loops are important:

• Loop 2: high-side MOSFET, Q1. During the high-side MOSFET turn-on, high current flows from the bootstrap

(boot) capacitor through the gate driver and high-side MOSFET, and back to the negative terminal of the boot

capacitor through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from

the gate of the high-side MOSFET through the gate driver and SW, and back to the source of the high-side

MOSFET through the SW trace. See also "loop 2" of Figure 7-22.

• Loop 3: low-side MOSFET, Q2. During the low-side MOSFET turn-on, high current flows from the VCC

decoupling capacitor through the gate driver and low-side MOSFET, and back to the negative terminal of the

capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from the gate of

the low-side MOSFET through the gate driver and GND, and back to the source of the low-side MOSFET

through ground. See also "loop 3" of Figure 7-22.

TI strongly recommends following circuit layout guidelines when designing with high-speed MOSFET gate drive

circuits.

• Connections from gate driver outputs, HO and LO, to the respective gates of the high-side or low-side

MOSFETs must be as short as possible to reduce series parasitic inductance. Be aware that peak gate drive

currents can be as high as 3A. Use 0.65mm (25mils) or wider traces. Use via or vias, if necessary, of at least

0.5mm (20mils) diameter along these traces. Route the HO, SW gate traces as differential pairs from the

LM25139 to the applicable high-side MOSFETs, taking advantage of flux cancellation.

• Minimize the current loop path from the VCC and CBOOT pins through the respective capacitors as these

provide the high instantaneous current, up to 3A, to charge the MOSFET gate capacitance. Specifically,

locate the bootstrap capacitor, CBOOT, close to the respective CBOOT, SW pin pair of the LM25139 to

minimize the areas of "loop 2" associated with the high-side drivers. Similarly, locate the VCC capacitor,

CVCC, close to the VCC and PGND pins of the LM25139 to minimize the areas of "loop 3" associated with the

low-side drivers.

7.4.1.3 PWM Controller Layout

With the provision to locate the controller as close as possible to the power MOSFETs to minimize gate driver

trace runs, the components related to the analog and feedback signals as well as current sensing are considered

in the following:

• Separate power and signal traces, and use a ground plane to provide noise shielding.

• Place all sensitive analog traces and components related to COMP, FB, ISNS+, and RT away from high-

voltage switching nodes such as SW, HO, LO, or CBOOT to avoid mutual coupling. Use internal layer or

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LM25139

SLVSJ80 – OCTOBER 2025

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