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layers as ground plane or planes. Pay particular attention to shielding the feedback (FB) and current sense

(ISNS+ and VOUT) traces from power traces and components.

• Locate the upper and lower feedback resistors (if required) close to the FB pin, keeping the FB trace as short

as possible. Route the trace from the upper feedback resistor to the required output voltage sense point at

the load.

• Route the ISNS+ and VOUT sense traces as differential pairs to minimize noise pickup and use Kelvin

connections to the applicable shunt resistor (if shunt current sensing is used) or to the sense capacitor (if

inductor DCR current sensing is used).

• Minimize the loop area from the VCC and VIN pins through the respective decoupling capacitors to the

PGND pin. Locate these capacitors as close as possible to the LM25139.

7.4.1.4 Thermal Design and Layout

The useful operating temperature range of a PWM controller with integrated gate drivers and bias supply LDO

regulator is greatly affected by the following:

• Average gate drive current requirements of the power MOSFETs

• Switching frequency

• Operating input voltage (affecting bias regulator LDO voltage drop and hence the power dissipation)

• Thermal characteristics of the package and operating environment

For a PWM controller to be useful over a particular temperature range, the package must allow for the efficient

removal of the heat produced while keeping the junction temperature within rated limits. The LM25139 controller

is available in a small, 3mm × 3mm 16-pin RGT PowerPAD™ integrated circuit package to cover a range of

application requirements. Section 7.4.1.4 summarizes the thermal metrics of this package.

The 16-pin RGT package offers a means of removing heat from the semiconductor die through the exposed

thermal pad at the base of the package. While the exposed pad of the package is not directly connected to any

leads of the package, the exposed pad of the package is thermally connected to the substrate of the LM25139

device (ground). This connection allows a significant improvement in heat sinking, and the PCB designed with

thermal lands, thermal vias, and a ground plane to complete the heat removal subsystem becomes imperative.

The exposed pad of the LM25139 is soldered to the ground-connected copper land on the PCB directly

underneath the device package, reducing the thermal resistance to a very low value.

Numerous vias with a 0.3mm diameter connected from the thermal land to the internal and solder-side ground

plane or planes are vital to help dissipation. In a multi-layer PCB design, a solid ground plane is typically placed

on the PCB layer below the power components. Not only does this action provide a plane for the power stage

currents to flow but this action also represents a thermally conductive path away from the heat generating

devices.

The thermal characteristics of the MOSFETs also are significant. The drain pads of the high-side MOSFETs are

normally connected to a VIN plane for heat sinking. The drain pads of the low-side MOSFETs are tied to the SW

plane, but the SW plane area is purposely kept as small as possible to mitigate EMI concerns.

7.4.1.5 Ground Plane Design

As mentioned previously, TI recommends using one or more of the inner PCB layers as a solid ground plane. A

ground plane offers shielding for sensitive circuits and traces and also provides a quiet reference potential for the

control circuitry. In particular, a full ground plane on the layer directly underneath the power stage components

is essential. Connect the source terminal of the low-side MOSFET and return terminals of the input and output

capacitors to this ground plane. Connect the PGND and AGND pins of the controller at the DAP and then

connect to the system ground plane using an array of vias under the DAP. The PGND nets contain noise at the

switching frequency and can bounce because of load current variations. The power traces for PGND, VIN, and

SW can be restricted to one side of the ground plane, for example on the top layer. The other side of the ground

plane contains much less noise and is an excellent choice for sensitive analog trace routes.

LM25139

SLVSJ80 – OCTOBER 2025

www.ti.com

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