TSC2004IRTJR datasheet(30/62 Pages) TI2

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START A WRITE CYCLE

WriteCycle

I CSlaveAddress

I C

Write-

AddressingByte

ACK

STOP

(1)

START

1 C3 C2 C1 C0 RM

ControlByte1

I C

SlaveAddress

I CWrite-

AddressingByte

ACK

STOP

(1)

STOP

(1)

A3 A2 A1 A0

ControlByte0

DataByte1/2

(HIGHByte)

DataByte2/2

(LOWByte)

A P

I C

SlaveAddress

I CWrite-

AddressingByte

MixedM(ControlByte1orControlByte0withReadBit)

PlusN(ControlByte0withDataBytes),SeparatedbyTSC ACKs

(M+Nx3)x8

A P

ConverterFunction Select

TSCInternalRegisterAddressforWriteData

I C

SlaveAddress

I CWrite-

AddressingByte

ACK

STOP

(1)

A3 A2 A1 A0

ControlByte0

A P

TSCInternalRegisterStartingAddressmh

(2)

START

FromMastertoSlave

A=Acknowledge(SDALOW)

N=NotAcknowledge(SDAHIGH)

S=STARTCondition

P=STOPCondition

Sr=RepeatedSTARTCondition

FromSlavetoMaster

NOTES: (1)Inordertostartthenextsequence,aSTOPconditionmustbefollowedbyaSTARTcondition.IfnoSTOPis

used,thenaRepeatedSTARTmustbeused.AlsonotethatisaSTOPconditionisissuedinHigh-Speed

mode,themodewillreverttothepreviousmode:FastorStandard.

(2)mhisahexadecimalnumber.

TSC2004

SBAS408E – JUNE 2007 – REVISED MARCH 2008

A write cycle begins when the master issues the slave address to the TSC2004. The slave address consists of

seven address bits and a write bit (R/W = 0; see Table 5). When the eighth bit has been received and the

address matches the AD1-AD0 address input pin setting, the TSC2004 issues an acknowledge bit by pulling

SDA low for one additional clock cycle (ACK = 0); see Figure 34.

When the master receives the acknowledge bit from the TSC2004, the master writes the input control byte to the

slave; see Table 5. After the control byte is received by the slave, the slave issues another acknowledge bit by

pulling SDA low for one clock cycle (ACK = 0). The master then ends the write cycle by issuing a STOP or

repeated START condition; see Figure 35.

Figure 35. Write Cycle

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