CC113LRGPR datasheet(41/87 Pages) TI2

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CC113L

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SWRS108B – MAY 2011 – REVISED JUNE 2014

5.14 RX FIFO

The CC113L contains a 64-byte RX FIFO for received data and the SPI interface is used to read the RX

FIFO (see Section 5.5.5 for more details). The FIFO controller will detect overflow in the RX FIFO.

When reading the RX FIFO the MCU must avoid reading it past its empty value since a RX FIFO

underflow will result in an error in the data read out of the RX FIFO.

Likewise, when reading the RX FIFO the MCU must avoid reading the RX FIFO past its empty value since

a RX FIFO underflow will result in an error in the data read out of the RX FIFO.

The chip status byte that is available on the SO pin while transferring the SPI header contains the fill

grade of the RX FIFO (R/W = 1). Section 5.5.1 contains more details on this.

The

number

bytes

the

FIFO

can

also

read

from

the

status

RXBYTES.NUM_RXBYTES. If a received data byte is written to the RX FIFO at the exact same time as

the last byte in the RX FIFO is read over the SPI interface, the RX FIFO pointer is not properly updated

and the last read byte will be duplicated. To avoid this problem, the RX FIFO should never be emptied

before the last byte of the packet is received.

For packet lengths less than 64 bytes it is recommended to wait until the complete packet has been

received before reading it out of the RX FIFO.

If the packet length is larger than 64 bytes, the MCU must determine how many bytes can be read from

the RX FIFO (RXBYTES.NUM_RXBYTES-1). The following software routine can be used:

1. Read RXBYTES.NUM_RXBYTES repeatedly at a rate specified to be at least twice that of which RF

bytes are received until the same value is returned twice; store value in n.

2. If n < # of bytes remaining in packet, read n-1 bytes from the RX FIFO.

3. Repeat steps 1 and 2 until n = number of bytes remaining in packet.

4. Read the remaining bytes from the RX FIFO.

The 4-bit FIFOTHR.FIFO_THR setting is used to program threshold points in the FIFOs.

Table 5-14 lists the 16 FIFO_THR settings and the corresponding thresholds for the RX FIFO.

Table 5-14. FIFO_THR Settings and the Corresponding

FIFO Thresholds

FIFO_THR

Bytes in RX FIFO

0 (0000)

1 (0001)

2 (0010)

3 (0011)

4 (0100)

5 (0101)

6 (0110)

7 (0111)

8 (1000)

9 (1001)

10 (1010)

11 (1011)

12 (1100)

13 (1101)

14 (1110)

15 (1111)

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