CC113LRGPR datasheet(47/87 Pages) TI2

47 / 87 page

CC113L

www.ti.com

SWRS108B – MAY 2011 – REVISED JUNE 2014

5.19 Asynchronous and Synchronous Serial Operation

Several features and modes of operation have been included in the CC113L to provide backward

compatibility with previous Chipcon products and other existing RF communication systems. For new

systems, it is recommended to use the built-in packet handling features, as they can give more robust

communication, significantly offload the microcontroller, and simplify software development.

5.19.1 Asynchronous Serial Operation

Asynchronous transfer is included in the CC113L for backward compatibility with systems that are already

using the asynchronous data transfer.

When asynchronous transfer is enabled, all packet handling support is disabled and it is not possible to

use Manchester encoding.

Asynchronous serial mode is enabled by setting PKTCTRL0.PKT_FORMAT to 3. Data output can be on

GDO0, GDO1, or GDO2. This is set by the IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG and

IOCFG2.GDO2_CFG fields.

In asynchronous serial mode no data decision is done on-chip and the raw data is put on the data output

line. When using asynchronous serial mode make sure the interfacing MCU does proper oversampling

and that it can handle the jitter on the data output line. The MCU should tolerate a jitter of ±1/8 of a bit

period as the data stream is time-discrete using 8 samples per bit.

In asynchronous serial mode there will be glitches of 37 - 38.5 ns duration (1/XOSC) occurring

infrequently and with random periods. A simple RC filter can be added to the data output line between

CC113L and the MCU to get rid of the 37 - 38.5 ns glitches if considered a problem. The filter 3 dB cut-off

frequency needs to be high enough so that the data is not filtered and at the same time low enough to

remove the glitch. As an example, for 2.4 kBaud data rate a 1 k

Ω resistor and 2.7 nF capacitor can be

used. This gives a 3 dB cut-off frequency of 59 kHz.

5.19.2 Synchronous Serial Operation

Setting PKTCTRL0.PKT_FORMAT to 1 enables synchronous serial mode. When using this mode, sync

detection should be disabled together with CRC calculation ( MDMCFG2.SYNC_MODE=000 and

PKTCTRL0.CRC_EN=0).

Infinite

packet

length

mode

should

used

(

PKTCTRL0.LENGTH_CONFIG=10b).

In synchronous serial mode, data is transferred on a two-wire serial interface. The CC113L provides a

clock that is used to sample data on the data output line. The data output pin can be any of the GDO pins.

This is set by the IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG, and IOCFG2.GDO2_CFG fields. The RX

latency is 9 bits.

The MCU must handle preamble and sync word detection in software, together with CRC calculation.

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