CC113LRGPR datasheet(74/87 Pages) TI2

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CC113L

SWRS108B – MAY 2011 – REVISED JUNE 2014

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Each decoupling capacitor should be placed as close as possible to the supply pin it is supposed to

decouple. Each decoupling capacitor should be connected to the power line (or power plane) by separate

vias. The best routing is from the power line (or power plane) to the decoupling capacitor and then to the

CC113L supply pin. Supply power filtering is very important.

Each decoupling capacitor ground pad should be connected to the ground plane by separate vias. Direct

connections between neighboring power pins will increase noise coupling and should be avoided unless

absolutely necessary. Routing in the ground plane underneath the chip or the balun/RF matching circuit,

or between the chip’s ground vias and the decoupling capacitor’s ground vias should be avoided. This

improves the grounding and ensures the shortest possible current return path.

Avoid routing digital signals with sharp edges close to XOSC_Q1 PCB track or underneath the crystal Q1

pad as this may shift the crystal dc operating point and result in duty cycle variation.

The external components should ideally be as small as possible (0402 is recommended) and surface

mount devices are highly recommended. Components with different sizes than those specified may have

differing characteristics.

Precaution should be used when placing the microcontroller in order to avoid noise interfering with the RF

circuitry.

A CC11xL Development Kit with a fully assembled CC113L Evaluation Module is available. It is strongly

advised that this reference layout is followed very closely in order to get the best performance. The

schematic, BOM and layout Gerber files are all available from the TI website (SWRR081 and SWRR082).

Figure 6-4. Left: Top Solder Resist Mask (Negative) – Right: Top Paste Mask. Circles are Vias

Applications, Implementation, and Layout

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CC113LRGPR Datasheet(PDF) 74 Page - Texas Instruments