CC2564MODACMOG datasheet(24/68 Pages) TI2

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Clock

Data_In

Frame_Sync

Frame period

Data_Out

Frame idle

Clk_Idle_Start

Clk_Idle_End

frmidle_swrs064

CC2564MODN, CC2564MODA

SWRS160E – FEBRUARY 2014 – REVISED JANUARY 2017

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Product Folder Links: CC2564MODN CC2564MODA

Detailed Description

5.8.4

Frame Idle Period

The codec interface handles frame idle periods, in which the clock pauses and becomes 0 at the end of

the frame, after all data are transferred.

The module supports frame idle periods both as master and slave of the codec bus.

When the module is the master of the interface, the frame idle period is configurable. There are two

configurable parameters:

•

Clk_Idle_Start: indicates the number of clock cycles from the beginning of the frame to the beginning of

the idle period. After Clk_Idle_Start clock cycles, the clock becomes 0.

•

Clk_Idle_End: indicates the time from the beginning of the frame to the end of the idle period. The time

is given in multiples of clock periods.

The delta between Clk_Idle_Start and Clk_Idle_End is the clock idle period.

For example, for clock rate = 1 MHz, frame sync period = 10 kHz, Clk_Idle_Start = 60, Clk_Idle_End = 90.

Between both Frame_Sync signals there are 70 clock cycles (instead of 100). The clock idle period starts

60 clock cycles after the beginning of the frame and lasts 90 – 60 = 30 clock cycles. Thus, the idle period

ends 100 – 90 = 10 clock cycles before the end of the frame. The data transmission must end before the

beginning of the idle period.

Figure 5-6 shows the frame idle timing.

Figure 5-6. Frame Idle Period

5.8.5

Clock-Edge Operation

The codec interface of the module can work on the rising or the falling edge of the clock and can sample

the Frame_Sync signal and the data at inversed polarity.

Figure 5-7 shows the operation of a falling-edge-clock type of codec. The codec is the master of the bus.

The Frame_Sync signal is updated (by the codec) on the falling edge of the clock and is therefore

sampled (by the module) on the next rising clock. The data from the codec is sampled (by the module) on

the falling edge of the clock

CC2564MODACMOG Datasheet(PDF) 24 Page - Texas Instruments

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