TAS5802PWPR datasheet(33/106 Pages) TI2

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6.5.2.2 Sequential Write

A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes

are transmitted by the master to the device as shown in Figure 6-13. After receiving each data byte, the device

responds with an acknowledge bit and the I2C subaddress is automatically incremented by one.

Figure 6-13. Sequential Write Transfer

6.5.2.3 Random Read

As shown in Figure 6-14, a single-byte data-read transfer begins with the master device transmitting a start

condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write

followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory

address to be read. As a result, the read/write bit is a 0. After receiving the address and the read/write bit,

the device responds with an acknowledge bit. In addition, after sending the internal memory address byte, the

master device transmits another start condition followed by the address and the read/write bit again. This time

the read/write bit is a 1, indicating a read transfer. After receiving the address and the read/write bit, the device

again responds with an acknowledge bit. Next, the device transmits the data byte from the memory address

being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop

condition to complete the single-byte data-read transfer.

Figure 6-14. Random Read Transfer

6.5.2.4 Sequential Read

A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are

transmitted by the device to the master device as shown in Figure 6-15. Except for the last data byte, the master

device responds with an acknowledge bit after receiving each data byte and automatically increments the I2C

subaddress by one. After receiving the last data byte, the master device transmits a not-acknowledge followed

by a stop condition to complete the transfer.

Figure 6-15. Sequential Read Transfer

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TAS5802

SLASFB7A – NOVEMBER 2024 – REVISED AUGUST 2025

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TAS5802PWPR Datasheet(PDF) 33 Page - Texas Instruments