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L6238S Datasheet(PDF) 10 Page - STMicroelectronics |
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L6238S Datasheet(HTML) 10 Page - STMicroelectronics |
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10 / 31 page  After the next align time-out 192/Falign), the con- troller enters the Go mode, were the sequencer again double increments the output phase upon detection of the motor’s Bemf. The align time-out may be optimized for the appli- cation by changing the Faling reference fre- quency. A Watch-Dog Timer protection feature is built into the control logic to monitor the Falign pin for a clocking signal. This circuitry, shown in Figure 2-3 will prevent start up the device if the Falign clock is not present. Without this feature, the output would remain in the first phase under high current conditions, if the clock were not present. If the external sequencer is used to provide start up, the system clock may be tied to the Falign pin to satisfy the requirements of the Watch-Dog Timer. 2.3 Resynchronization If power is momentarily lost, the sequencer can automatically resynchronize to the monitored STATE = 1 DRIVERS OFF MIN CLOCK DELAY PERIOD STOP DELAY STOP MASK STOP SEQLNC=1 & OUTENA=0 RUN/BRK=X INT. START-UP DISABLED MIN. CLOCK DELAY LOAD MIN. DELAY LOAD MIN. MASK*** RUN/BRK=1 & OUTENA=1 DRIVERS ON PERIOD COUNT DELAY COUNT STATE=STATE+1* MASK COUNT MASK COUNT SEQINC=0 SEQINC=1 LOAD DELAY=PERIOD LOAD MASK=PERIOD RESET PERIOD PERIOD COUNT DELAY COUNT** BEMF BEMF SEQINC=0 SEQINC=1 RUN/BRAKE=1 RUN/BRAKE=0 FROM ANY STATE DRIVERS OFF MIN CLOCK DELAY LOAD MIN MASK*** PERIOD STOP DELAY COUNT STATE=STATE+1 MASK COUNT LOAD MIN. DELAY LOAD MIN. MASK*** DELAY COUNT STATE=STATE+1 MASK COUNT BEMF STATE=STATE+1 SEQINC=1 RETURN TO PREVIOUS STATE (CHANGING SEQINC=1) BEMF FROM ANY STATE WITH SEQ_INC=0 * VALID IF SEQINC=0, AND DELAY TIMES OUT ** CLOCK DELAY=F(TDLY_[2:0]) WHEN BEMF PERIOD <3.3ms @ 10MHz (SPEED >12.7Hz FOR 8 POLES) STATE=STATE+2 CHECK FOR Zc BEMF DRIVERS OFF STATE=STATE+1 MIN CLOCK DELAY LOAD MIN DELAY LOAD MAX MASK DELAY COUNT STATE=STATE+1 MASK COUNT OUTENA=1 OUTENA=1 OUTENA=1 DRIVERS OFF MIN CLOCK DELAY PERIOD STOP DRIVERS ON PERIOD STOP DELAY STOP MASK STOP STATE=STATE+2 STATE=STATE+1 LOAD DELAY=MIN LOAD MASK=MAX PERIOD COUNT DELAY COUNT STATE=STATE+1 MASK COUNT BEMF LOAD DELAY=MIN LOAD MASK=MIN RESET PERIOD PERIOD COUNT DELAY COUNT* STATE=STATE+1 MASK COUNT 221 SYS_CLK 221 SYS_CLK DRIVERS OFF RUN/BRK=0 DRIVERS OFF RUN/BRK=0 DRIVERS ON LOAD DELAY=PERIOD LOAD MASK=PERIOD RESET PERIOD PERIOD COUNT DELAY COUNT* STATE=STATE+1 MASK COUNT DRIVERS OFF MIN CLOCK DELAY PERIOD STOP OUTENA=0 BEMF MONO=0** BEMF OUTENA=1 OUTENA=1 BEMF ALIGN & GO MODE RESYNCHRONIZATION MODE RUN MODE * CLOCK DELAY=F(TDLY [2:0] WHEN BEMF PERIOD <3.3ms @ 10MHz (SPEED>12.7Hz FOR 8 POLES) BEMF: BEMF RISING WITH PNSLOPE=1 OR BEMF FALLING WITH PNSLOPE=0 BEMF1: BEMF RISING WITH PNSLOPE=0 OR BEMF FALLING WITH PNSLOPE=1 **MONO=0 WHEN FREQ(BEMF)=2*FREQ(PHASE) ***MIN MASK=192/SYS_CLK(I.E. WITH SYS_CLK=10MHz,MIN MASK=19.2 µs) D95IN280 192/FALIGN 64/FALIGN OUTENA=0 221 SYS_CLK OUTENA=0 OUTENA=1 BEMF POR=0 FROM ANY STATE (FOR IS GENERATED INTERNALLY BY MONITORING VLOGIC) Figure 2-1 L6238S 10/31 |
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