Dual Universal Switched-Capacitor Filters

4

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PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

FILTER

Center Frequency Range

fO

Mode 1

0.001 to

40

kHz

Clock-to-Center Frequency

Accuracy

fCLK/fO

Mode 1, R1 = R3 = 50k

Ω , R2 = 10kΩ,

Q = 5, deviation from 100:1

±0.2

±0.7

%

Q Accuracy

Mode 1, R1 = R3 = 50k

Ω, R2 = 10kΩ,

Q = 5

±0.2

±2%

fO Temperature Coefficient

±1

ppm/

°C

Q Temperature Coefficient

±5

ppm/

°C

DC Lowpass Gain Accuracy

Mode 1, R1 = R2 = 10k

Ω±0.1

±0.5

%

VOS1

DC offset of input inverter

±3

±12.5

VOS2

DC offset of 1st integrator

±4

±15

DC Offset Voltage

(Figure 8)

VOS3

DC offset of 2nd integrator

±4

±25

mV

Crosstalk (Note 2)

fIN = 10kHz

-60

dB

Input: COM externally driven

VDD/2

- 0.1

VDD/2

VDD/2

+ 0.1

COM Voltage Range

VCOM

Output: COM internally driven

VDD/2

- 0.1

VDD/2

VDD/2

+ 0.1

V

Input Resistance at COM

RCOM

60

80

120

k

Ω

Clock Feedthrough

Up to 5th harmonic of fCLK

200

μVRMS

Noise (Note 3)

Mode 1, R1= R2 = R3 = 10k

Ω,

LP output, Q = 1

60

μVRMS

Output Voltage Swing

0.2

VDD - 0.2

V

Input Leakage Current at COM

SHDN = GND, VCOM = 0 to VDD

±0.1

±10

μA

CLOCK

Maximum Clock Frequency

fCLK

4

MHz

EXTCLK = GND, COSC = 1000pF

95

135

175

kHz

Internal Oscillator Frequency

(Note 4)

fOSC

EXTCLK = GND, COSC = 100pF

1.35

MHz

Clock Input High

VDD - 0.5

V

Clock Input Low

0.5

V

Clock Duty Cycle

50

±5%

SHDN AND EXTCLK

Input High

VIH

VDD - 0.5

V

Input Low

VIL

0.5

V

Input Leakage Current

VINPUT = 0 to VDD

±0.4

±10

μA

ELECTRICAL CHARACTERISTICS—MAX7491

(VDD = VEXTCLK = +3V; fCLK = 625kHz; 10kΩ || 50pF load to VDD/2 at LP_, BP_, and N_/HP_; VSHDN = VDD; 0.1µF from COM to

GND; 50% duty-cycle clock input; COM = VDD/2; TA = TMIN to TMAX. Typical values are at TA = +25°C, unless otherwise noted.)

(Note 1)