AD4086BBCZ datasheet(36/91 Pages) AD

36 / 91 page

Data Sheet

AD4086

DIGITAL INTERFACE

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Rev. 0 | 36 of 91

ISTER_ACCESS options as demonstrated in the examples shown

in the Instruction Mode Selection section and the Strict Access

Selection and Multibyte Registers section.

Instruction Mode Selection

The configuration interface memory controller defaults to streaming

mode upon power up (SINGLE_INST = 0). In streaming mode, mul-

tiple, contiguous registers are accessed in a single SPI frame, start-

ing at the address specified in the instruction phase. In streaming

mode, only one instruction phase is permitted per SPI frame, requir-

ing a new SPI frame be initiated for changing access commands

or otherwise access a noncontiguous address in the register space.

For each byte transferred during the subsequent data phase, the

internal address counter is automatically updated according to the

setting of the ADDR_ASCENSION bit in the Interface Configuration

A register (see the Interface Configuration A Register section), in

the way specified by Table 15.

Table 15. Address Ascension Selection

ADDR_ASCENSION Bit

Value

Address Controller Behavior

(STRICT_REGISTER_ACCESS = 1)

0 (Default)

Decrement Address. Multibyte registers are accessed

by addressing the most significant byte address.

Increment Address. Multibyte registers are accessed

by addressing the least significant byte address.

Figure 61 illustrates the generic SPI frame formatting for a serial

transaction using the default interface configuration. In this exam-

ple, a portion of the configuration register space consisting of

a byte-wide register and a multibyte register is accessed. The

address for the byte-wide register resides in the most significant

address (ADDRESS) and the most significant byte of the multibyte

segment. By default, the ADDR_ASCENSION property is set to

descending, indicating that the address for the most significant

phase. Depending on the selected operation, the instruction word

is followed by either a payload consisting of data for the byte-wide

bytes (MSBYTE) of the multibyte register, or, in the case of a

read access, padding bits. As a convention, it is recommended to

pass Logic 1 to SDI during a read access to avoid accidentally

addressing address zero for write access.

In single instruction mode (SINGLE_INST = 1), the memory access

controller requires an instruction phase to transmit for each register

accessed in a given SPI frame as illustrated in Figure 62. This

mode is useful when access to nonadjacent sections of the register

space is required in a given SPI frame. Note that, the same access

flexibility can be achieved in stream mode by initiating a new SPI

frame for each unique register access.

The single instruction mode is selected by setting SINGLE_INST

= 1 in the Interface Configuration B register (see the Interface

Configuration B Register section, Address 0x01).

Figure 61. Interface Access Example, Default Interface Configuration, Streaming Mode (ADDR_ASCENSION = 0)

Figure 62. Interface Access Example, Single Instruction Mode (SINGLE_INST = 1), All Other Interface Options Default

AD4086BBCZ Datasheet(PDF) 36 Page - Analog Devices

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