AD4086BBCZ datasheet(47/91 Pages) AD

47 / 91 page

Data Sheet

AD4086

DIGITAL INTERFACE

analog.com

Rev. 0 | 47 of 91

Table 20. Valid LVDS_CNV_CLK_CNT Settings

LVDS_CNV_CLK_CNT

Settings

Clock Count Number

Single Lane Mode

Dual Lane Mode

0b0000

0b0001

0b0010

1/5

0b0011

0b0100

Selection not valid

0b0101

Selection not valid

0b0110

Selection not valid

As a overview guide, Table 21 indicates the minimum required

LVDS_CNV_CLK_CNT settings for various conversion rates.

The maximum tMSB of 22.4ns, that is with the gain error correction

enabled (see the Gain Error Correction section), is used for all

calculations in Table 21.

On power-up, the value of the gain error correction is 0x200,

disabling the correction and allowing for a lower latency result. In

this case, tMSB is 18 ns and a latency of 48.21 ns can be achieved.

To aid alignment of this valid result data position with the digital host

of the user, the ADC Data Interface Configuration A register (see

the ADC Data Interface Configuration A Register section, Address

0x15) contains access to the interface check feature enabled by

setting the INTF_CHK_EN bit. When this bit is set, the ADC results

are no longer output on the interface, and the output is replaced

with a fixed pattern 20b1010 1100 0101 1101 0110 (0xA C5D6).

This feature allows the user to align and test the data interface to

their digital host. When the INTF_CHK_EN bit is unset, the normal

conversion results are output to the LVDS interface immediately.

This method is useful for alignment, particularly for self clock mode

cases where unknown PCB propagation delays may be present

between the AD4086 and its digital host controller. Note that this

feature was specifically designed to help output LVDS data with the

LVDS clock of the digital host by using static data, and the feature

does not indicate if the LVDS_CNV_CLK_CNT setting is used.

Table 21. LVDS_CNV_CLK_CNT Settings for Various Sample Rates (with gain correction applied)

Sample Rate (MSPS)

LVDS Lanes

fCLK (MHz)

tCLK (ns)

(tMSB/tCLK) + 1.5

LVDS_CNV_CLK_CNT Setting

280

3.571

7.772

245

4.082

6.988

210

4.762

6.204

175

5.714

5.420

140

7.143

4.636

105

9.524

3.852

140

7.143

4.636

LVDS Data Transfer Latency

Where the user is concerned in knowing the overall latency from

when an individual ADC conversion is initiated to the time when

the LSB has reached the host controller, it is important to consider

the data transfer latency. The total latency observed is the sum of

the ADC latency and the data transfer latency, in this case, the

LVDS_CNV_CLK_CNT is set to achieve minimum ADC latency.

Additional clock cycles more than the minimum required incur

additional LVDS clock cycles of latency to the overall latency, as is

shown in Figure 76.

The data transfer latency on the LVDS interface depends on the

following parameters:

►

LVDS clock period, tCLK

►

Number of active LVDS lanes, NLANES

►

Number of bits to be read, NBITS

Calculate the latency as follows:

Data

Transfer Latency= NBITSNLANES×tCLK

For applications that require extremely low latencies, note that as

the data is transferred MSB to LSB in both single and dual lane

modes, and that there is no requirement to fully read a result from

the interface, the data transfer latency can be reduced for lower

resolution results (that is, NBITS can be chosen to be smaller than

the maximum 14 bits available).

AD4086BBCZ Datasheet(PDF) 47 Page - Analog Devices

AD4086BBCZ Datasheet(HTML) 47 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

Datasheet Download

Link URL