AD4086BBCZ datasheet(38/91 Pages) AD

38 / 91 page

Data Sheet

AD4086

DIGITAL INTERFACE

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Rev. 0 | 38 of 91

Figure 63. Generic Byte Wide Memory, Multibyte Register Example

As indicated in Figure 64, the address counter, by default, automat-

ically decrements (ADDR_ASCENSION = 0) such that the most

significant byte of the multibyte register is accessed first, followed

by the remaining byte(s) in that register in ascending order. Con-

versely, if ADDR_ASCENSION = 1, the least significant byte of the

multibyte register is accessed first followed by most significant byte.

As an extension of this concept, when STRICT_REGISTER_AC-

CESS = 1, any SPI frame that accesses a multibyte register as

the first entity in the data transfer must correctly set the starting

address in the instruction word to correspond to the ADDR_AS-

CENSION selection. In the case that the address counter automat-

ically decrements (ADDR_ASCENSION = 0), the starting address

is assigned to the register address for the least significant byte of

that multibyte register, and conversely, if configured to increment

automatically, the starting address must be set to the register

address for the most significant byte. As a result of the change

to ADDR_ASCENSION from automatic address decrement (0) to

automatic increment (1), Figure 61 and Figure 62 will change as

illustrated in Figure 64 and Figure 65 to accommodate the changes

in data phase byte order and instruction phase multibyte register

start address.

Figure 64. Single Instruction Format, ADDR_ASCENSION = 0 (Descend), STRICT_REGISTER_ACCESS = 1 (Enabled)

Figure 65. Single Instruction Format, ADDR_ASCENSION = 1 (Increment), STRICT_REGISTER_ACCESS = 1 (Enabled)

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